Itty bitty O-scope probes

I can't follow your thinking here. Regardless of what you are controlling, clocks are always sensitive to signal integrity and everything you listed is driven by a finite state machine (FSM). Clock glitches in a FSM can cause it to skip over states or to jump to wrong or even illegal states.

I think what you mean to say by "low speed" is logic where you don't care if it screws up. I suppose it would be hard to notice if an LED skipped an off state and stayed on twice as long or if an occasional PWM pulse were missing when it controls a motor.

But calling it "low speed" or even mentioning speed as a factor is very much a misnomer.

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Rick C

Sounds like dramatic overkill. Next time I set up a probe fixture using the bus wire I'll take a photo or two.

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Rick C

We use testpoints on all nodes so full ICT test is supported

I keep asking for less testpoints and replace ICT by functional test, but we won't get the same test coverage

Cheers

Klaus

I worked on an array processor many years ago. The used a 16 layer board with an embedded "omega" layer for the ECL terminations. The via holes were just the right size to let us remove the probe clip and stick the small probe tip into the via. Only problem was they were both fragile and expensive. After some time we broke enough of them they switched to low cost probes that made our job much harder in every way.

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Rick C

Yeah pogo-pins is what I added to an x-y-z stage.

George H.

Look how much money we're saving, boss! Gee -- it's too bad that the circuit designers have suddenly gotten really inefficient at debugging...

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Tim Wescott 
Wescott Design Services 
http://www.wescottdesign.com 

I'm looking for work -- see my website!

I gave up inserting test points. I never used them (no one else did, either) and they took too much space (silk). Probe "shields" aren't the answer, either. I try not to use SOICs (changing opamps to TSSOPs now).

Nice! That's like what I did with my RF probe amplifier. You can use a pogo pin for the earth connection for better contact (the BF862 FET buffer is on the other side):

If I silver-soldered the probe tip I could make it quite a lot shorter than the 4mm you see here. As it is, this is flat to

350MHz, and I suspect the limit is in the amplifier (though that simulates well to 800MHz, there are obviously strays omitted).

Actually, if Win Hill sees this, perhaps he might comment on the likely primary cause of the frequency limit? All the design files are in the directory that contains that image. I'd like to improve it if I knew where to start.

Clifford Heath.

I use a set of these (TPI version)

Power on/off when hooking up. PCB TP a must now adays.

cheers

This wasn't design. This was production test. We had to build the damn things and they wouldn't tell us everything they did. One of the schematic blocks had a caption, "who knows what this does". The machine was poorly designed for timing and required custom tuning of clock wires (twisted pair connecting across the backplane) to get it to work. Then the field service guys would have to do a lot more than replace boards to fix a broken machine.

That wasn't what killed the company though. They built a half speed version in a single card cage which was used in CT scanners and sold well. But DSP chips were coming out and they couldn't adapt. Sort of like the main frames and minicomputers they were attached to.

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Rick C

I think scope makers provide probe tip covers that protect the tip from shorting adjacent pins, at least for DIP size parts. Not sure how well it would work on finer pitch parts.

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Rick C

Proof of concept worked, I'll probably use epoxy next time. New SMD SOIC-W ? memory chip, the sort with short pins bend down , so no horizontal lands for soldering to, thought a more stringent test.

With a rule bent the pins upwards to give needle hole positions. Stretched plumbers ptfe over the chip, pins puncturing the ptfe. Stretched some ptfe spaghetti tube and cut 3mm long pieces, 1 over each pin, and flowed hot melt over the top and pins in a bund, not the bottom so I could remove the IC after

The BFR93A is indeed a nice RF transistor. It's not fT that we care about (Cbe), but rather Ccb. At low voltages Ccb increases to about 1pF (see the Infineon datasheet). In your circuit we have Q2 and Q3 plus some wiring capacitance, call it 1pF, or 3pF total, against R3 = 220 ohms. That works out to -3dB at 240MHz. If you're getting 350MHz, you're ahead of the game!

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 Thanks, 
    - Win

Try hot melt glue instead of epoxy. I use it for everything. I just repaired my construction boots with some: I also repaired a difficult to sew rip in a laptop bag.

In production test fixtures, I would drill a slab of thick PCB material for pogo pin sockets. However, I would NOT make it a tight fit. I would then align the BUT (board under test) with the slab and hot melt glue the pogo pin sockets in place so that they hit exactly on the pad or trace. This was especially handy because most of the boards were 3D affairs, not just 2D.

The real headache were the alignment holes on the BUT. I would put 2 or 4 alignment holes on the layout, and the PCB house would solder plate the hole. Assembly would later plug the holes with solder. I asked to have them solder masked, which was fine until someone decided that it cost to much. I never did solve the problem. Every time I needed test fixture alignment holes on the boards, something went wrong.

Another fun problem was that we use the production test fixture to make environmental measurements in a test chamber. The hot melt glue did well on the hot side, but would lose its grip on the pop pin sockets when really cold (below about -10C). I managed to destroy a few fixtures that way. Epoxy would have survived, but was not suitable for re-heating and adjusting the position of the pins.

Also, be careful what flavor of hot melt glue you use. Some of the stuff is mildly conductive.

--
Jeff Liebermann     jeffl@cruzio.com 
150 Felker St #D    http://www.LearnByDestroying.com 
Santa Cruz CA 95060 http://802.11junk.com 
Skype: JeffLiebermann     AE6KS    831-336-2558

Last weekend I too repaired a shoe with hotmelt. This trial memory chip guard jig, 1.25mm/.05inch spacing. Second go with hotmelt, lightly rubbed the ptfe over the pins, with fine sandpaper, before piercing thru. Used ordinary fine polyester sleevingthis time, fitted to a pin and cutting to length in place is much easier than placing short precut lengths on small pins

Awesome, thanks! And here I was suspecting the probe inductance.

I'm not sure where the LTSpice simulation went wrong, but I'm guessing it wasn't looking at Ccb properly.

So it sounds like the best bet is to reduce R3 to 68 ohms (losing headroom), perhaps run higher current (up to 30mA from 20 - max is

35mA though) to get back some of the lost headroom, and maybe increase Vcc to 12V or more to reduce Ccb (and change bias to suit). It sounds like I can crank this over 500MHz or better, which would be sweet.

Any other pointers?

By the way, the new AoE has been my bed-time reading for several months now - very much appreciated. I never had a copy of AoE2.

Clifford Heath.

Either you read slower than I do, or you fall asleep way faster. ;)

Cheers

Phil Hobbs

Probably both, but usually I'm too tired by the time I get bed. Plus, I never studied most of this stuff at university, so I've read many sections several times.

Clifford Heath.

I often fall asleep in my chair and wake up at 2 AM, so I understand.

All my bedtime reading happens in the morning. ;)

Cheers

Phil Hobbs