Interpreting Datasheet switching times for MMBTA06

Hello Jeff,

Well, that figure is a timing diagram. Td is the delay time and Ts is the storage time, sometimes also called Tstg. It take time to move carriers in and out, where "out" is the real challenge in bipolar transistors. Sometimes that requires the 'sledge hammer' method by pulling the base negative as much as safely possible. Another more effective trick is to prevent saturation altogether by 'robbing' base current just before the transistor reaches that point. This is done via a Baker Clamp where a Schottky diode robs the base current as the Uce approaches 200mV.

Regards, Joerg

How much gate swing do you need, and what's the effective gate capacitance? How fast do you want to go? There are some ICs that would maybe do the job a lot easier that building your own gate driver.

John

Hello John,

Or use a pnp/npn push-pull pair to swing the gate if there is enough drive voltage but not enough oomph. That works quite zippy.

Best would be if Jeff could post a schematic.

Regards, Joerg

Thanks!

I had heard of storage time before but somehow had a mental block on Ts (duh!). I had it in the back of my mind that storage time was more related to base current rather than collector current too so maybe thats the reason for my block... Its been 15yrs since I sat in a lecture on any of this stuff. This is starting to make more sense now. The transistor takes about 3us from when the base drive goes low before we see the collector start to rise. I've calculated the Ic in the circuit and see that it actually falls off the low end of that timing curve. The Td is 1us for 15mA Ic (lowest Ic that Ts is defined and min value on the entire plot is 5mA) and I think we have >1us for our Ic. I am thinking this part is not the best choice for this application with such low collector currents.

Jeff

Hello Jeff,

That's too high. Something else must be going on. Does the FET have a large gate capacitance?

Td should be under 200nsec here so I guess there is something else in the way. Can you post a schematic? Doesn't have to be the whole enchilada, just the drive circuit and what it's driving.

Regards, Joerg

Hi. Unfortunately, I can't post any diagrams.

The MMBTA06 is set up as a common emitter or open collector inverter and the collector pulls down on a circuit with another MMBTA06 NPN with a MMBTA56 PNP wired as a current amp in a emitter follower. Those are arranged to turn on some p channel fets (2 in parallel). The total Ciss of those is about 7000pF. There are 2 resistors and a zener that set the gate voltage referenced to the incoming power voltage. Resistor divider is connected to the common bases of the NPN/PNP. The zener is to make sure that Vgs of the fets stays 30v. The NPN/PNP pair are just there to boost the source/sink current of the divider. The p channels are used to switch power on or off to another circuit.

I mistyped when I said Td was 1us on the curve for 15mA. I mean't Ts. The Ts curve falls off the graph for current under 15mA so being at 2mA I think Ts has to be >1us and could explain the slow turn off.

The p fets turn on pretty fast (

Hello Jeff,

If for legal reasons, ok. Else just take a digital camera and then post it on a.b.s.e. or some free web site. Maybe your employer can give you a little 'scratch area' on their site (usually they won't).

That's hard to decipher, even a hand-sketch would make things much easier. I don't quite get how the current amp can turn on the p-channel FETs. Anyway, 7000pF is a whole lot of capacitance for that poor MMBTA06 to drive.

That's a situation I deal with a lot, the designer not being there anymore. Most important is not to rely on device parameters to achieve a minimum like your new 3usec spec. Best is to have a device or circuit that is much faster and design in a reliable delay such as RC followed by a Schmitt. Or two ping-pong delays if on and off times must be different. At those speeds you could probably even use a little motor driver half-bridge chip as a driver.

Regards, Joerg

Uh-huh, too lazy? Even proprietary stuff can safely have a snippet posted, ASCII drawing, etc., especially if it's simple commonplace circuitry and one is seeking advice about it.

It seems Jeff's driving them with a push-pull emitter-follower pair.

It would appear he's in a scene where the datasheet switching-time parameters are irrelevant, compare to the other circuit parameters.

Let's help the poor drawing-impaired fellow out. (As usual, Jeff, use a fixed font like Courier to view the drawing.)

. . ------+------+-------+---------, . | \\_|_ | | . Rup /_\\ | | . | | |/ NPN | . +------+-----| | . | | |\\v | . | | | |--S . Rdn | +-----|| p-channel . | | | |--D MOSFETs . | | |/v | . |/ NPN '-----| '---- . ---| |\\ PNP . |\\v | . | . gnd

We need corrections to my drawing, and resistor + zener values. The 'A06 and A56 transistors are capable of providing 150-200mA of gate drive output, if they have sufficient base drive. 150mA into 7000pF would move the gate voltages at i/C = 21V/us, or 0.6us to move 12V. It appears Jeff's seeing a slower time, so he may benefit from more base drive. If he reduces the values of Rup and Rdn, he can increase the current and speedup the MOSFET shutoff, down to the 0.5us limit of the A06 and A56 capability (they weren't a good choice, due to a poor high-current beta falloff, but they may be sufficient for Jeff).

Redesigning to use a decent MOSFET driver IC would be a good idea.

Well, you got it pretty close....

. ,------+--------+---------+----VOUT . | \\_|_ | | . 10k /_\\ 15v | | . | | |/ NPN | . +------+------| |___, . | | |\\v | | . | | | |--S _ . 10k | +-----|| ^ p-channel . | | | |--D | MOSFETs . | | |/v |___| . |/ NPN '------| | .-4.7k-+-- +---| |\\ PNP '----VIN=9--32v . | | |\\v | . 10k C1 | | . | | gnd gnd . gnd gnd

The circuit seems a little odd since the FETs appear to be in backwards relative to Vin and Vout. Its intentional for reasons I can't get into too far. Suffice to say this thing is supposed to act like a rectifier under some circumstances and a short under others.

The cap C1 is what I have added to increase the FET turn-on delay from

That's a common approach to making an active-assisted power diode. The MOSFET's substrate diode insures that the output follows Vin if it's positive, and when you turn on the drive the voltage drop will be reduced if Vin is high enough and the FETs are big enough.

Well, you can reduce the two 10k driving resistors by say 3 to 4x, right? And if you tack on a reverse diode across the 4.7k you'll rapidly discharge the added 2700pF. Check the resulting slight slowing of the input pulse's falltime won't bother something else.

Well, one can pull current out of the base without the use of a negative voltage supply. Alter the base drive and use a resistor in series from driver to NPN base. Add a PNP; the base tied to the driver, collector to ground and emitter to the base of the NPN...one could also try the inverted configurationby interchanging the emitter and collector.

Hello Robert,

IIUC this wouldn't be able to pull the base closer than 600mV to GND since the pnp is wired as an emitter follower.

To obtain sufficient charge removal without negative supply I usually employ a capacitor. Depending on the duty cycle and avaliable swing that does the job. Of course, the other option would be to use one of those gold-doped npn transistors. They don't have a lot of beta but they sure blaze. Nowadays they aren't that expensive anymore.

Regards, Joerg