Formulas for this circuit?

It's a Pierce oscillator, so I think the frequency will be dominated by the parallel LC circuit. C2 and C3 are effectively in series, so won't have much effect. You could check by simulating it with SPICE.

Leon

The LC resonant frequency is approximately 1/(2*pi*sqrt(LC)), except that C is C1 in parallel (added to) the series combination of C2 and C3 which is 1/((1/C2)+(1/C3)). It is approximate, because it neglects the capacitance of the input of the NAND gate and stray capacitance.

The resistor is often found by experiment. The higher the resistance, the higher the Q of the resonance (purer frequency) but the smaller the signal at the input of the gate, so the more rounded the output wave, or even lack of oscillation. The selection of C2 and C3 are also related to the loop gain of the oscillator. They usually work best if equal, but one, effectively includes the input capacitance of the gate, so the capacitor shown is smaller than the other.

Unless you need really high frequencies, use 4093 (including Schmitt triggers at all inputs) instead of 4011. Independently, you don't need two-input gates for this. You can use either 40106 (6 inverters with Schmitt trigger) or 4049UB.

The exact oscillation frequency depends (among other things) on the input threshold voltage of the gate. I would run a simulation.

Best,

Not only- but clearly wrong advice. It was what the clueless OP deserved nonetheless. Also, IIRC the entire idea stunk as the LC resonance coincided with the abrupt cut-off frequency of the buffered CMOS.