interesting jfet

Am 02.06.23 um 19:34 schrieb John Larkin:

I prefer On Semi CPH3910. I paralleled 16 of them. More bang (less voltage noise) per buck.

Gerhard

Encouraging that they’re bringing it out in 2023. The matching is very good, and the 1/f corner is excellent.

Wiring them in parallel basically gets you a $3 CPH3910, only slower.

I’m not sure that I believe 1 nV noise with only 10 mS gM

Cheers

Phil Hobbs

It might be interesting to run a couple of packages in parallel, to get lower noise while keeping the good matching. That would avoid having to use op amp bandaids on discrete pairs to get decent DC performance, which we have to do sometimes.

What does it mean for a product to be a "Burr-Brown" at this point? It's unclear to me from the document if this is an actual new product, or a re-released old product, or if "Burr Brown" is just like a trim-line marketing moniker at this point, like buying a Chrysler New Yorker with the "Mark Cross package."

TI acquired b-b in 2000. Some parts are still considered to be in the b-b division, but I don't know if that has a physical meaning. It may just be a trademark now, mostly for audio parts.

I asked TI for support on a different part, and the guy said "That's a Burr-Brown part, we don't know much about it."

Yes, diff pairs in parallel would be good too, if you really need diff.

I like the clamp diodes; I might use it just for them.

There's probably some dumb CMOS part that accidentally has pA or fA clamp diodes. I've used a DG408 analog mux just as an 8-channel rail clamp.

Not much point otherwise, unless the somewhat-better 1/f corner is a big deal in a given application. CPH3910s are quieter in the flatband, at

The low noise at indifferent gM is interesting, though. An ideal BJT’s noise temperature is Tj/2, compared to 2/3 Tj for an ideal JFET.

An ideal BJT at 0.25 mA Ic has a gM near 10 mS, so its-Hz voltage noise is ideally

sqrt(0.5 * 4kT/gM), about 0.9 nV.

An ideal JFET with the same gM has sqrt(1.5) times more, about 1.1 nV, which is close to what TI claims.

However, that doesn’t leave much space for the resistance of the silicon and wiring. So using a few packages in parallel makes some sense.

It sounds as though they pulled something out of the BB files and re-implemented it on a modern process with good JFETs.

Pretty cool, in 2023.

Cheers

Phil Hobbs