Hi,
I was thinking about how to minimize switching losses and also on state resistance, as well as having reduced gate driver requirements, and was thinking this would be a good idea:
use 1 fet with very fast rise/fall times as well as low gate charge (but high on-state resistance)
then the rest of the parallel fets rise/fall times as well as gate drive requirements are almost irrelevant. As long as they switch within say 100ns they will relieve the single fet which hopefully fully switched within 10ns, and then had normal Rds(on) losses for 90ns. Then for 100kHz switching, the other lower Rds(on) fets would take all the load for 10us, while the other "pulse" fet has a chance to cool down until the next 100ns switch point.
So the benefits are reduced gate drive current requirements, and not having to find fets that have BOTH low Rds(on) as well as low gate charge and fast rise/fall times.
Another idea I was thinking, to use a zero ohm resistor on the single fast fet, as the gate ringing may not matter on that fet as long as it is able to stay turned on for at least 100ns before the ringing turns it off.
Would these ideas be practical?
cheers, Jamie