Intel tri-gate finFETs

Actually, their instructions sets are just as large, if not larger than CISC. They're all very simple instructions, though.

They also claimed that those ran faster so more of them would still get you to point B faster.

We have plenty of IC chip real estate these days. We can pre or post process anything invisibly.

What does the current Cray use? The Cell (Power PC) or Intel CORE?

I'll bet it isn't RISC. Hell, it wouldn't surprise me if it didn't move to Graphics GPUs for the job. How small are those instruction sets?

You probably did not even ever look at the CELL CPU.

I wonder if the 6502 would qualify. It had a very nice, orthogonal instruction set, where "page 0" (0x00 - 0xff) was practically a set of 256 registers, but the stack was entirely contained on "page 1" (0x100 - 0x1ff), so you couldn't make very deep calls and it wouldn't have been very "C-friendly."

But I loved it! I used one in(as?) a controller for a raw keyboard (individual spst switches), and it was a snap! ASCII existed at the time, so the 6502sent ASCII keystrokes to my Z-80-based "TV Typewriter." :-)

Oh, for the "good old days!"

Cheers! Rich

The next step will probably be many-core (like, 256 maybe) ARM cpu's with some serious hardware security features.

John

Sounds vaguely like the 8008, whose instruction set was almost microcode.

Thanks! Rich

"Reduced instruction set computing", actually.

Sometimes, but you still come out ahead, because each instruction executes in one clock, and the instruction decoding is all in hardware, instead of a microinstruction store.

If the compiler wants a complex instruction, it just makes one from a string of simple ones. That will execute as fast as an old multi-cycle CISC instruction, maybe faster.

John

Remember "The Connection Machine?" It was a whole shitpot-load of little processors (like 256 or 65536 or so), but apparently it died because nobody could figure out how to write software for it.

Cheers! Rich

Multicore is easy to program. Run the OS on one core, and each task or thread or driver on its own core. Power down the ones that aren't busy.

Just stop thinking of CPUs as being valuable.

John

No, the stack in memory, alone, would disqualify it.

Nah, these are the good ol' days. Someone else does that grunt work. ;-)

Not at all! Not enough registers and it did have memory ops, IIRC.

Reduced Instruction Set Complexity, was what it was supposed to be.

That usually works, though even PowerPC went to multi-cycle instructions (and all the rest of the CISCy things) because the clock just got too fast to keep up the single-cycle mantra.

Multicore is insanely difficult to program.

Sure. There is some 256 cores or so on the video card. Do some programming; then tell us how it does.

Just stop thinking.

Vladimir Vassilevsky DSP and Mixed Signal Design Consultant

John,

What is exactly your issue with x86 ?

What makes you thinking that the replacement of x86 to ARM would change anything ?

:)))

Vladimir Vassilevsky DSP and Mixed Signal Design Consultant

Why don't you two just get a room at the nearest No-Tel?

It's ancient, klunky, and a power hog. And the combination of Windows and x86 is a national security risk. Buffer and stack overflow exploits should be flat impossible on any sensible architecture. Neither Microsoft nor Intel seems to have ever figured out that one shouldn't execute data.

John

You haven't paid much attention to their latest architectures then.

National security risk? You're an idiot.

You are only about 5 years behind the curve, John.

Hi,

Know of any ARM micro's that have 3 or more DAC outputs? It seems multichannel ADC's are common but multi channel DAC's are harder to find in microcontrollers.

cheers, Jamie

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Now that it is possible to have multiple CPUs on a single chip, why could they all be identical. A few could run x86 code, some PowerPC codes and some for instance ARM codes ? It would be natural to run different virtual machine operating systems on these.

Of course this can cause some problems with memory management (e.g. different virtual memory page sizes).