Intel announces Atom CPu with Altera FPGA in one housing

Pins? On one chip?

How about a 32-bit wide DPM running at CPU speed? There's no way you're going to beat that.

Exactly. That's why they had to use an existing serial bus.

I don't know of any cases of serial busses being used to communicate between sections of a single chip.

If we could get an ARM+FPGA+Gbit ethernet on one chip, we'd buy it right now.

John

Reply to
John Larkin
Loading thread data ...

...and pass the costs onto the customer. IOW, they didn't have the business case to do it right. It's a hack.

Reply to
krw

formatting link

Good point. It's insane to use Intel chips in anything that you hope to manufacture for more than a year or so. Intel has been known to heavily promote embedded processors and cancel them before production even starts.

John

Reply to
John Larkin

in

development

yeh, pins or a new combined chip design

of course not, but afaik only the cpu and cache that runs at cpu speed so that would require quite a bit of surgery

and at 1.6GHz it would have to be some pretty fast memory

neither have I, but I guess at some point when it gets big enough it might start to make sense

I've put an arm7tdmi-s in a xilinx FPGA several times when I made asic prototypes though it was quite big and only ran at ~24MHz, which was what I needed

didn't Altera have and arm7 for their FPGAs at one point?

for xilinx theres always ppc or microblaze

-Lasse

Reply to
langwadt

formatting link

Not to worry as Intel gives the actual design tools and documentation for top line embedded processors only to the chosen ones. That Atom/Altera combo is probably designed by request of the particular user like Apple or such.

VLV

Reply to
Vladimir Vassilevsky

Which in turn causes many to wait until it's not "bleeding edge" and this in turn reduces the market even more, spiraling toward cancellation even further.

This reminds me of TV shows where they cancel 2 years into a 4 year story arc. People actually start getting shy about "getting into" a new show for fear they'll be left hanging.

In turn, even more stuff is geared toward short attention spans.

It's a bad feedback loop.

Reply to
Greegor

in

development

We're planning a product that needs GbE and an FPGA. Looks like the best combo may be a PPC for $12 and an outboard Altera chip, with a memory-mapped parallel interface.

John

Reply to
John Larkin

But most any serial protocol ends up being packet-based with CRCs and extra latency relative to a parallel bus... and it's a lot easier to route a half-dozen 2.5Gbps differential traces around a board than constructing a big parallel bus that provides the same overall bandwidth.

For applications where you need lots of bandwidth but some latency is OK and there's tons of memory around to load up devices drivers, handle enumeration, etc. PCIe can work just peachy...

Remember how big ultra/wide SCSI cables were? -->

formatting link
... and that was only

40MBps!
Reply to
Joel Koltner

If that makes such business sense, then it makes more sense to keep the two designs separate, and have two pairs of tracks between the two, in terms of yield and risk, an ultimately price.

Reply to
Fredxx

Last time I checked, Freescale was still making MC68332s, and had no plans to EOL them. After about 20 years.

They made the original 6800 (nmos, depletion load, 1 MHz) for about that long.

John

Reply to
John Larkin

Exactly. It's not like you're saving a lot of second-level package pins. This product makes no sense at all.

Reply to
krw

memory,

PCIe does not have latency issues with CPU and memory comms. The whole damn bus was created to INCREASE speed and throughput between the graphics card and the CPU and memory. So compared to any other glue yet out there (on x86), it is thus far the fastest.

It is its own bus (PCIe).

PCI is its own bus, and ALL other interfaces are tertiary to the PCI bus EXCEPT for AGP (obsolete) and now PCIe.

AGP just wasn't quite enough.

Now that it is here though, folks are looking at and using it for other high data rate devices like SAS drive array cards, etc.

USB 3.0 should be fun. Now one would think that there would be considerable latency with comms thru that bus/interface.

Reply to
TheGlimmerMan

You are a hack on the industry.

They integrate it with an Nvidia GPU and make PCs out of 'em.

I don't think they'd have any trouble gearing this chip up right. They are quite small in size (the dies).

The bus is fine for the task. The idiots that think there is a problem are the hacks.

Reply to
TheGlimmerMan

formatting link

They sold the arm.

But you should likely at least cite when you make a remark like that.

Reply to
TheGlimmerMan

Ha! We're doing 10GbE designs now.

Look for PCIe Gen-2 stuff too.

Reply to
TheGlimmerMan

And look how small SAS is and the drives too!

15k rpm! Put that in your array and spool it up!

Serial Attached SCSI is where it's at!

Reply to
TheGlimmerMan

I see you're off your meds again, AlwaysWrong.

Reply to
krw

Oooops... restored, asshole!

You are a hack on the industry.

They integrate it with an Nvidia GPU and make PCs out of 'em.

I don't think they'd have any trouble gearing this chip up right. They are quite small in size (the dies).

The bus is fine for the task. The idiots that think there is a problem are the hacks.

KeithkiethStain is a retard... Yeah, that's you, Williams.

Reply to
WhySoSerious?

We?

John

Reply to
John Larkin

Board, yes. Chip, no.

John

Reply to
John Larkin

ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.