insane flipflop measurements

If the error code is E5622, the most common one, the fix is to replace the sram things in the bottom. That's easy.

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I have maybe 10 of the mainframes and a couple dozen heads, worth a fortune at the original price. Beautiful instruments. My personal scope is an old b+w 11802, which takes nicer pics than the later color versions. It will internal trigger, too, with the delay lines.

Anybody interested in picosecond stuff should get one of these. They do weigh 50 lbs or so.

--

John Larkin         Highland Technology, Inc 
picosecond timing   precision measurement  

jlarkin att highlandtechnology dott com 
http://www.highlandtechnology.com
Reply to
John Larkin
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Very. L-trimmed surface mount resistors have much less inductance and parallel capacitance.

--
Bill Sloman, Sydney
Reply to
bill.sloman

Analog Devices ADCMP580 CML output comparator. (maybe adcmp590 or so, I cannot check it here). I do like CML!

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I had faster ones, but they are not on the open market. Laser drivers.

(JL, sorry if I happened to shock you, but note the half year waiting time for the ON semi parts!)

Gerhard

Reply to
Gerhard Hoffmann

Digikey has a couple hundred in stock. We have most of a 3K reel.

We use it as a mosfet or phemt gate driver too. It's a pretty good deal for 16 cents.

--

John Larkin         Highland Technology, Inc 

lunatic fringe electronics
Reply to
John Larkin

Change the circuitry to have balanced Q/_Q drive to two otherwise identical in layout parts and look at the outputs. Betcha you see decidedly different timings. Then swap the layouts and note that difference essentially does not change...

Reply to
Robert Baer

Maybe. But then why is the one edge reasonable? Is its true rate appallingly slow (>1ns)?

What does it do between SET and (D=0) CLK?

Tim

--
Seven Transistor Labs, LLC 
Electrical Engineering Consultation and Contract Design 
Website: http://seventransistorlabs.com
Reply to
Tim Williams

The falling edge, the slower one, is 488 ps. The rise seems to be genuinely about 200 ps, using the HP probe.

I'm not planning to use SET, but I'd expect it to be similar to clear.

--

John Larkin         Highland Technology, Inc 

lunatic fringe electronics
Reply to
John Larkin

I don't see a Tr or Tf spec in the data sheet. The 2.5 ns, in one figure, seems to be a max for the clock input.

Tr and Tf are seldom specified for logic or FPGAs.

--

John Larkin         Highland Technology, Inc 

lunatic fringe electronics
Reply to
John Larkin

This thing was a 32-channel "discriminator" for nuclear signals. It had two comparators and a scheme to compare a delayed and attenuated signal with the original, to achieve a measure of rise-time compensation. Called, in that field, a "constant fraction discriminator". So, each of the 32 sections had a power island with caps and a series resistor for decoupling. I just measured the dip in voltage when it switched, and was astounded to see a huge dip in voltage. Yes, there are all SORTS of parasitic inductances in the decoupling caps that makes real quantitative numbers pretty suspect.

Yes, quite likely the voltage inside the chips was massively affected, if I saw that much dip at the outside.

Oh, I assumed that any attempt to measure it had an error bar of about +/-

50% or worse. But, it told me I had FOUND the problem, and I just had to find chips that didn't have such horrible shoot through.

Jon

Reply to
Jon Elson

Hmm, you're right, the waveform on page 7 is labeled CP Input (

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).

Definitely nothing in that data sheet to suggest transition times in the hundreds of ps. It would be funny if it turned out that cheap carbon film resistors act like shock lines.

-- john, KE5FX

Reply to
John Miles, KE5FX

Den tirsdag den 31. januar 2017 kl. 05.08.21 UTC+1 skrev John Larkin:

you should be able to get the all "real" numbers from the ibis file

this isn't right part number but it was the first I found

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look at around line 16967 for falling waveform at 5V

Reply to
Lasse Langwadt Christensen

Well, that's unlikely. Somebody would have noticed by now.

I repeated the tests with the HP resistive, 6GHz, probe, and it looked about the same.

The Q and Qbar outputs look about the same.

This is really cool:

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--

John Larkin         Highland Technology, Inc 
picosecond timing   precision measurement  

jlarkin att highlandtechnology dott com 
http://www.highlandtechnology.com
Reply to
John Larkin

Then try it with a different scope.

Reply to
Tom Del Rosso

I'm using a nice LVDS->CMOS receiver chip that has typical rise and fall times in that range, according to a datasheet plot of t_R vs C_load. (I'm not at my computer or I'd post a datasheet link.)

Of course that's at very low C_load.

Cheers

Phil Hobbs

Reply to
pcdhobbs

Are LVDS outputs balanced? AIUI "differential" means positive and negative voltage, but "balanced" means equal and opposite current. So if the swing is 0 to 5 on each line then it might be balanced if the source and sink currents are equal, but differential means the swing is, say -5 to 5. If those definitions are right, then what's the purpose of differential signals that aren't balanced?

Reply to
Tom Del Rosso

Yes, they are balanced.

The output structure is usually drawn as a current steering pair, but that's a lie: there's a fairly low common mode impedance in there. A necessity, in fact!

Engineers so often follow, blindly, into the belief that differential = magic solution. But no, you can't fool the signal. Exceed the input CM range and your signal goes bye-bye!

Having a high-ish CM output impedance, does two things:

  1. It passively DC biases the output, so Vcm = Vdd/2.
  2. It provides some damping for the transmission line: as opposed to a perfect CCS, which will permit high-Q resonances on the line (making the system very sensitive to AC upset).

The CM impedance being higher than most CM transmission line impedances, isn't ideal for the most common use case (LVDS pairs on PCB have a pretty low Zcm, maybe 50 ohms), but does help with worst-case "accidents" (you should never run a non-isolated pair through space alone, but if you do -- for example by using a ribbon twist cable -- the high Zcm of that condition will be terminated even better).

Note also that, since the source is a high impedance, and the load(s) are high impedance (there's no CM termination in the standard), an LVDS bus looks like a 1/2 wave resonator, so at least the first resonant mode falls at a higher frequency than if it were driven with a very low impedance logic driver (which would make a 1/4 wave resonator).

And yes, the output pin pair is carefully synchronized, so that little common mode AC voltage is transmitted -- the currents match.

LVDS (and compatible standards) I think is the only case where Vcm is allowed to float, at a fairly high CM compliance.

Other differential standards nail down Vcm firmly: RS-422/485 transmitters are simply pairs of logic buffers, one complemented (422's outputs are always on, 485 is tristateable; 485 also has diodes in series with its output transistors, so it won't clamp line voltage to the rails, and can be powered down without loading the line). The Z_CM of a 422/485 transmitter is quite low indeed (~20 ohms?), which can give rise to standing waves during transmission.

Or Ethernet PHYs, which are just open drain pins, actually; they require source termination resistors, and the isolation transformer is obligatory for success (and EMI reduction!) over any distance.

Or CAN PHYs, which drive the terminated line through diodes (like an RS-485 transmitter, but instead of a full H-bridge, it's one diagonal pair, so the "negative" line state is 0V instead of negative), so Vcm can be wide if undriven (wide noise margin), but is firmly nailed to Vdd/2 during transmit (which can cause standing waves).

Tim

--
Seven Transistor Labs, LLC 
Electrical Engineering Consultation and Contract Design 
Website: http://seventransistorlabs.com
Reply to
Tim Williams

It's a FIN1002. Fairchild are being poopyheads and encrypting their datasheets for some reason, but you can get it from AllDatasheet: . Check out Figure 19.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs 
Principal Consultant 
ElectroOptical Innovations LLC 
Optics, Electro-optics, Photonics, Analog Electronics 

160 North State Road #203 
Briarcliff Manor NY 10510 

hobbs at electrooptical dot net 
http://electrooptical.net
Reply to
Phil Hobbs

Am 02.02.2017 um 17:13 schrieb Phil Hobbs:

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Gerhard

Reply to
Gerhard Hoffmann

The 11802/SD24 has 20 GHz bendwidth, and it looks perfect using the calibrator pulse and its own TDR step. I see about the same waveform using the resistor pickoff vs the 6 GHz HP probe on the other sampling channel.

That 150ish ps rise looks real. Amazing for a 16 cent CMOS part.

--

John Larkin         Highland Technology, Inc 

lunatic fringe electronics
Reply to
John Larkin

In that datasheet it's Figs 20 and 21.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs 
Principal Consultant 
ElectroOptical Innovations LLC 
Optics, Electro-optics, Photonics, Analog Electronics 

160 North State Road #203 
Briarcliff Manor NY 10510 

hobbs at electrooptical dot net 
http://electrooptical.net
Reply to
Phil Hobbs

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