Initializing a Flip-Flop on Power-up

You are on the right track. Surf on POR or "power on reset".

...Jim Thompson

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|  James E.Thompson, P.E.                           |    mens     |
|  Analog Innovations, Inc.                         |     et      |
|  Analog/Mixed-Signal ASIC\'s and Discrete Systems  |    manus    |
|  Phoenix, Arizona            Voice:(480)460-2350  |             |
|  E-mail Address at Website     Fax:(480)460-2142  |  Brass Rat  |
|       http://www.analog-innovations.com           |    1962     |
             
     It\'s what you learn, after you know it all, that counts.

"Dan Charette" schreef in bericht news: snipped-for-privacy@4ax.com...

Disconnect R or S from ground, depending on what you want, reset or set. Connect a 10uF cap between +V and this input. Put a 47K or 100K resistor between input and ground.

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Thanks, Frank.
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Use something like this to generate a reset pulse:

Only one part required. BTW, don't let the "microcontroller" in the description throw you, they are suitable for POR of any 3-5V CMOS logic circuit.

While you can use an RC (typically about 0.1s time constant with a diode to help out the protection diode to Vdd, a series resistor to limit the current in case of a Vdd-to-ground short, and perhaps a drain resistor from Vdd to Vss to make sure that Vdd falls reasonably quickly), it's far from foolproof, more complex and not much cheaper. Another low-cost solution is to use a zener, a BJT and a few resistors, with or without the RC, but that consumes more power, and is even more complex.

Hello Spehro,

My circuit du jour is a BSS123. Drain tugs on input that needs reset low. Gate has cap to VCC and resistor to GND. Plus discharge path if some BOR is required as well. If the 4-5c are too much I'll sometimes use a BJT. There must be a discharge path from VCC to GND if power is turned off. If there isn't that needs some extra parts.

Regards, Joerg

Here's a good start:

That will work, but I unless your power supply is very slow to ramp up, a

0.1 uF will work. If that is too many parts, just connect a small capacitor, 22 - 100 PF, from the Q or Q^ output to ground on the side of the FF that you want to come up in the 0 state. Note that both of these schemes may be unsuitable for production,and may not work during a brown out; for that you would need a power reset chip with a defined threshhold.

Tam

I'm throwing my hat in with Frank on this one. This is way overkill for what the OP wants.

I wouldn't use 10 uF, however; 1 uF is way more than enough - heck, what's the time constant of 1 nF and 100K?

And an "R" or an "S" input doesn't need a lot of noise immunity - once it's reset, it's reset! ;-)

Cheers! Rich

Hello Rich,

Ahem, if it's not a Schmitt input then rather bizarre things can happen when applying the ramp of a slowly charging cap. Stuff like both Q and /Q being high at the same time and occasionally that is followed by something that can't take that and croaks. Like an H-bridge.

Regards, Joerg

"Joerg" schreef in bericht news:m7qJf.21743$ snipped-for-privacy@newssvr14.news.prodigy.com...

Yeah, and the H-bridge was in charge of keeping the sattelite in orbit.

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Thanks, Frank.
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For an audio amplifier you can justify using a pot and spare 4093 adjusted to change state at Vcc/2; the 4093 holds the FF RST at low voltage and pulls 4013 R low for Vin>Vcc/2. This assumes Vcc/2>=2V or maybe 3V. FF S input is tied to GND.

"Joerg" schreef in bericht news:wvoJf.21712$ snipped-for-privacy@newssvr14.news.prodigy.com...

If there is no discharge path of importance, the 4013 stays in position for weeks. If there is a load on the power supply, the cap gets discharged through the internal protection diode.

Spending an extra 4-5 cents doesn't sound like you, what have you been drinking this afternoon? ;)

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Thanks, Frank.
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Hello Frank,

Yes, with CMOS this cane become a concern. I have had designs that could have properly idled for hours on a bunch of bypass caps.

Oh, just coffee. But not the Douwe Egberts brand :-(

It's a toss-up between cost and battery life. The BJT needs some base current. Only for a second or two but it can matter. Also, you need one additional resistor to avoid frying the base on power-up and this adds almost a cent back into it. So, if you can haggle the FET down to under

3c it'll break even. A lot of times I use the same FET for boost conversion and stuff like that and when there are no BJTs anywhere else it can be cheaper to use a FET for POR even if it's over 3c, by lower inventory and rigging costs.

So far the discrete solution was always more economical than one of the ritzy POR chips. Until one comes out that does it for around 5c.

Regards, Joerg

[snip] [snip]

Douwe Egbert makes coffee too? I used to smoke their Cavendish until the management decreed no smoking in the new house ;-)

Personal opinion: Anyone who relies on an edge detector for POR is a bit of a fool. In recent months it's been an almost weekly event to patch some chip that won't POR properly.

I prefer a level detect with hysteresis AND delay... easy to do if the chip design includes my bandgap reference ;-)

...Jim Thompson

--
|  James E.Thompson, P.E.                           |    mens     |
|  Analog Innovations, Inc.                         |     et      |
|  Analog/Mixed-Signal ASIC\'s and Discrete Systems  |    manus    |
|  Phoenix, Arizona            Voice:(480)460-2350  |             |
|  E-mail Address at Website     Fax:(480)460-2142  |  Brass Rat  |
|       http://www.analog-innovations.com           |    1962     |
             
     It\'s what you learn, after you know it all, that counts.

Did any of you guys even read the original question?

---------- From: Dan Charette ... I've got a small toggle circuit that I'm using to drive a shutdown circuit on an audio power amplifier. The circuit is made from a CD4093 Schmitt trigger NAND configured as a debouncer for my mute switch input. The output of the 4093 is fed into a CD4013 fo provide toggling cabability. I've got S and R tied directly to ground. But, I'd like to explore the possiblity of providing a predictable power-up scenario. Currently, the circuit upon power up will default to one state or the other. What are some methods that you fellas have used to achieve a known state consistantly with a flip-flop like this when the power supply is from a single source. First gut instinct that I'm thinking is to make some sorta RC timing circuit on the power supply pin so that I can provide the set or reset pins with something known before the power supply pin comes up. Any thoughts? Also, I don't want to add too much additional circuitry... if I can solve this purely with passive components or a few transistors, that'd be great. ...

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i.e., a small cap from Vdd to R, and a 47K-100K from there to Vss.

If you want to be persnickety about it, then Dan could see if there's a spare gate in his 4093

Or, better yet, put the R/C on one of the 4093 inputs - I'd have to see the existing circuit to see if that's doable.

Thanks! Rich

No, what was it?

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Thanks, Frank.
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Hello Jim,

Ah, a pipe smoker. Did that in my 20's for a couple years, on and off. Usually Skandinavik Mixture or Irish tobaccoes. That, and a nice glass of single malt.

IIRC coffee is Douwe Egbert's mainstream product. But Frank would know better, it's been two decades since I lived in the Netherlands. And I always liked the other brand better, Kanis&Gunninck or something like that.

Agree. It's pathetic what young engineers consider a POR these days. It's actually sad that they have to make a distiction between POR and BOR. Every reset should be good enough on brown-outs. What's really sad is that even our (rather expensive) Motorola cordless phone appears to perform dirty resets on occasion. Got enough honey-do projects so I am not going to fix their design.

When VCC is low or the circuits are picky I use a BJT because it makes for a better threshold. Or a TLV431 but that's expensive. If there is a regulator I take it off before that and after, then issue the reset before it is too close to dropout.

Us circuit designers have to pay extra for that bandgap. But a hysteresis is a good thing though I have to confess that I sometimes forego it, but only if there is enough margin between threshold and the circuit actually conking out. Plus enough decoupling capacitance to tide it over the reaction time.

Regards, Joerg

I smoked primarily Dutch Cavendish from age 18 to age 54.

I live the fun life... if I need a bandgap I just roll one... designed one last week that consumes only 5uA and comes fully alive at 1.5V input. Includes a POR.

...Jim Thompson

--
|  James E.Thompson, P.E.                           |    mens     |
|  Analog Innovations, Inc.                         |     et      |
|  Analog/Mixed-Signal ASIC\'s and Discrete Systems  |    manus    |
|  Phoenix, Arizona            Voice:(480)460-2350  |             |
|  E-mail Address at Website     Fax:(480)460-2142  |  Brass Rat  |
|       http://www.analog-innovations.com           |    1962     |
             
     It\'s what you learn, after you know it all, that counts.

I bet. This kind of thing can cause annoyance and much more serious things in the field.

How does your bandgap compare with published single/double bandgap references? Curvature correction PTAT term added?

Hello Jim,

Makes me drool. Often I envy you guys, maybe I should get into chip design some day. The few that I was involved in were lots of fun. But the SW tools we used were freaking expensive and had a steep learning curve even though someone else did the layout in all cases.

There was always that adrenaline rush during fab time. Will it work? What if the data input turns out to be deaf? What if we pushed the design rules too far this time? Tossing and turning at night. Luckily they did work. Whew.

Regards, Joerg