Infineon's CoolSic MOSFETs - a notch up.

Some of the SiC data sheets have a time-limited higher than steady-state max gate voltage. So maybe a few ns of over/undershoot is OK, just enough to slam the output edge.

The EPC GaN fets seem to have a gate overvoltage damage mechanism that can take hours or days to accumulate, somewhere between max specified gate voltage and Vgid, instant death. I wonder if SiC has anything like that. The time-limited spec suggests so.

So the optimum speed enhancer is... a series gate inductor!

Never approved by who?

That circuit assumes the lowside fet will be turned off for a known time, at low duty cycle. That's the case in a Pockels Cell pulse picker.

I'm relying on stern warnings appearing in vendor literature at design time; I haven't tried it.

Cheers, James Arthur

I've blow out the Cree parts by going too high on gate drive, maybe 25 volts at basically DC with low impedance drive, the bottom fet in a pulse generator.

The Infineon app note does state you can never exceed the max rating (20V) of the SiC:

So the 18V signal in the Dropbox link combined with the peaking of the indu ctor has to stay below that. Beyond that, the datasheet page 3 states that for proper lifetime rating, derate max ratings to 80%, so that would actual ly call for a 16V max gate voltage..

Cheers

Klaus

Right, if the gate waveform falls within limits (static and dynamic), it's fine. "Optimum", you might even say.

You sure are awfully proud of that series peaking inductor...

Tim

Heh, heh.. uhh, "MOS" and "MOV" are very different things!

Tim

Just trying to help.

If the peaking results in critical damping, the actual/internal gate voltage doesn't overshoot, it just rises faster. The Miller feedback makes it a little more complex. Like in a transmission line, the inductor adds time delay but stores energy for later use.

Are SiC fet sensitive to ESD then?