Infineon's CoolSic MOSFETs - a notch up.

Ultra-high-speed switching is out of my league, so excuse me this stupid question, but... If Rg is the limit, then why don't you increase the V_GS to say 100V and let things charge a bit faster? Of course, you would need to stop doing that rather quickly, but the initial current blast might be useful if the gate can survive that.

Where am I wrong?

Best regards, Piotr

That would probably blow out parts of the chip, near the gate contact but before the spreading resistance. Some data sheets suggest that extra gate voltage is OK at low duty cycle, which is one reason I like to add a bit of series inductance, to make a short overshoot spike.

That's a cheap (add one small inductor) and fairly safe equivalent of your idea, to overshoot the gate drive very briefly on both edges, to blast through the gate RC time constant.

One problem with commercial gate drivers, even nominally fast ones, is that they usually have outrageous propagation delays.

Mine was simple, two little EPC GaN fets. It's on a little throwaway mouse-bite baby board, to allow rework.

That is sure a wide input spec, explains it :-)

Overengineering is good sometimes. I once did Space electronics, and everything was overdesigned

Cheers

Klaus

Please do!

Thanks

What John said.

Even if you overvoltage the input insanely hard you have to back off so quickly to avoid killing the SiC FET that it hasn't gotten you much speed advantage -- the gate drive still has to propagate down the 25 ohm distributed Rg, charging the 200pF distributed Cgs, which was by far the greatest part of the whole delay in the first place.

(To a first order, Rg x Cgs = 25 ohms x 200pF = 5ns, an insuperable obstacle.)

That's what I meant by "Rg limited."

That's not the case for ordinary silicon, where people have gotten big speed ups from extreme over-drive for short times.

Doing this to either family voids the warranty; doing it to SiC voids the device :).

Cheers, James Arthur

I think that's proprietary Highland Technology magic!

Cheers, James Arthur

If the set a spec and the engineers are expected to exceed it, how much beyond the spec are they expected to achieve? Why not just set the spec to what is wanted???

I recall in training we were told that requirements saying things like, "X must be achieved but Y is desired" is of no value in a spec. X is what is needed. If Y is not required it has no place. I Y is required, use Y, not X.

If you design something so 99% of it will continue to operate for 99 years upside down in freezing temperatures all outside the spec, but one part fails... what good was it to get 99% of it to work?

This is why we have clear, well defined, testable requirements.

But... but... he said he could show it.

Yes, to me, which was generous. But he didn't say he could post it publicly. Of course, it's his choice.

I know a few of Highland's secrets. In thirty years I've never leaked. If he posted to s.e.d., would you promise not to tell?

Cheers, James Arthur

Oh all right, here's the lowside driver.

The highside is a lot more interesting.

Certainly, we can share anything. If it turned out to be really original and commercially useful, we might want to talk a little more, maybe share a few megabucks.

ad.

erything was overdesigned

eyond the spec are they expected to achieve? Why not just set the spec to what is wanted???

The project I worked in we did a subsystem, and only knew of the other syst ems via the overall system spec.

In general for Space you need to design using the JPL derating guides

I couldn't find it straight away, but stumbled over a worst case parameter shift table, page 93 and forward:

For the JPL guideline, Power is generally derated to 50%, voltage to 80%, c urrent to 80% for most parts. Curious is that connectors are not derated so heavily, which my guess is the reason is that voltages and currents in int erfaces are well know. For a commercial product where statistical probabili ty of a stupid user doing something odd, or a lightning strike etc will dri ve those specs. Lightning and users are not present in space :-)

Found a short summary for it:

X must be achieved but Y is desired" is of no value in a spec. X is what i s needed. If Y is not required it has no place. I Y is required, use Y, n ot X.

s upside down in freezing temperatures all outside the spec, but one part f ails... what good was it to get 99% of it to work?

In our derating we expect that something funny will happen, and in a parts per million case. Thus that improbable case should be covered. But in real life, what bites you is what you cannot predict, production f-ups, alternat ive setups of products, SW bugs etc

Cheers

Klaus

Well, no.

Consider this drive network:

| +---||--+ C | | | | Driver o--+--RRR--+--o Gate | R1 | | R R2 | R | _|_

Set C * (R1 || R2) = Rg * Ciss(eff). What do you get? :)

It's wasteful, sure, but if you want maximum possible speed, that's a price you're willing to pay.

The particle physics people have been doing this for a long time, saving on stages of magnetic compressors by overdriving IGBTs. As the drive current is higher, they tend to use more complicated active circuits.

Tim

The miller current is a lot more dominat, right?

For the Infinion type, you need at least 15V, so gate charge is 6nC. If you have 22 ohms from 15V to 5V, that's 500mA. At 6nC that is 12ns platau delay, that needs to be added.

One VERY significant feature of the gatedrive is the ability to keep the gate in control during the OFF period, if a large dV/dt voltage is present on the drain node

A design with a inductor to speed up the gatedrive would never be approved where I work. To much reliance on component spreads

Cheers

Klaus

That instantly kills a SiC MOSFET. Even marginally exceeding Vgs(max) is *not* allowed.

Speedup techniques like that work with silicon devices because those can tolerate massive overvoltages without failure. SiC cannot.

Cheers, James Arthur

Depends on the slew. i(Miller) is about 35mA at 50V/ns for the Infineon part, twice that at 100V/ns, etc.

Rg and Cgs are distributed, so it's not quite that bad--near parts of the FET will be enhanced long before the gate drive propagates to the distant die portions. Also, the part starts switching at Vgs=6V, long before 6nC, which helps, and you do not need 15V, only 12V.

But you can see that Rg definitely limits speed.

With a silicon FET, exotic applications just blast it with a huge overvoltage, but SiC's don't survive that.

Yes, discussed above w.r.t. to unipolar drive.

You could and can swamp the parasitics with external components and solve that, but it's not likely you'd have this set of needs in the first place.

Cheers, James Arthur

Is that certain? SiC has been used for decades in lightning arrestors. It might matter greatly what the gate construction is, but bulk SiC is ... robust.

Thanks, John.