Improve PWM outputs with S/H?

whit3rd · 2017-09-13T10:21:34+00:00

A simple timer can set a pin HIGH for N clock cycles out of 1024, then LOW for 1024 - N clock cycles. That output pin, with some RC filtering, generates about the same range and precision of voltages as a 10-bit DAC. But, cheaper. It also has ripple, because the filtered output ramps UP while the pin is high, and DOWN while low, dithering around the intended value, in addition to slowly (exponentially) decaying to a new average output value when a change is made. The RC time constant ought not to be made too long, or a change won't propogate quickly, but cannot be made too short, or the ripple will grow to be more than an LSB of the output. If one were, however, to use an analog switch in a sample/hold amplifier, taking a sample at N/2 cycles and/or at N + (1024-N)/2, the hold value would both ramp as quickly as the RC time (give or take half the PWM cycle period), AND would be devoid of the triangle-wave-like ripple. So, the idea is to change from one PWM output, to a PWM output and a two-pulse strobe auxiliary output. Then an external S/H amp can buffer the PWM aerage value, while rejecting the PWM ripple (because the strobe selects the centerpoints of rise and fall phases). Does a cheap (?quad) S/H chip exist to support this? Have any of the usual controller chips ever had an output option like this?

Sep 13, 2017 24 Replies

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whit3rd 9 years ago

On Thursday, September 14, 2017 at 4:09:51 AM UTC-7, Tim Williams wrote: [about sample/hold sampling of a PWM+filter triangle wave]

Two scenarios where this is NOT illlusory: a reference voltage, to be amplified for a DC power supply. Some stepping during a transition is acceptable, but driving high AC ripple into a (capacitive?) load is not. Or a trim voltage adjustment, which stays steady after power-on.

It is assumed that the phase is predictable: for a PWM signal with 1MHz clock, and 1 kHz cycle time, and a given RC filter, it is an easy optimization to calculate.

True. Another case for a S/H scheme is the problem of accurately measuring a slow (2 Hz) sinewave (or reasonable facsimile); a rectify-and-filter would take an egregious settling time, Sample/hold on a peak or trough, however, gives good accuracy, precisely because you CAN select, sometimes, a sample period for low amplitude fluctuation (good precision) or for good adherence to an ideal (the PWM ratio times a reference).

In both cases, the benefit is to get down to DC from an AC input, without settling-time of a simple lowpass filter.

It looks like there just ISN'T a jellybean low-cost/low-performance sample/hold or track/hold solution, though. Switch, driver, op amp, and some hold capacitor... it's gonna take up some board area.

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Jasen Betts 9 years ago

use a fast PWM.

say an 8 bit timer/counter in the AVR clocked at full clock speed set the most significant bits of the value in the PWM register in an interrupt service routine use whatever method to reverse low bits to decide when to dither the PWM value to

+1 - you only have to make this computation every 256 cycles, so so long as you can do in in fewer than 200 instructions (I estimate under 20 needed) there should be room to run code oustside of the ISR too.

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Lasse Langwadt Christensen 9 years ago

Den torsdag den 14. september 2017 kl. 13.09.51 UTC+2 skrev Tim Williams:

even a 1st order S-D converter has noise shaping, if you write out the transfer function from input to output it is an all-pass, from the comparator to the output is a high pass

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