PWM Output With RC Coupled Inverted Signal

We discussed Woodward's idea in Oct 2019 and Win Hill put it into the X-Chapters AoE book. Here is my saved EDN article:

piglet

Here is what Win posted 11 Oct 2019 from the then unpublished book:

"You could take a look at the x-Chapters section,

4x.25 Ripple Reduction in PWM, where we explore Stephen Woodward's clever ripple-reduction trick. "

You should buy the X-chapters book.

piglet

prove the filter response time of an RC filtered PWM signal by adding a ser ies RC from the inverted signal. The series RC did not impact the DC level of the output, but greatly improved the filtering.

from simulation or measurement with a scope.

fu just isn't working.

Yeah, that's good. With the date I was able to find the thread and the lin k to Win's dropbox.

Thanks,

--

Rick C. 

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The technique is basically a notch filter, similar to a twin-tee.

By all means get the X-chapters!

--

John Larkin      Highland Technology, Inc 

The best designs are necessarily accidental.

250 Hz is a pretty slow PWM, even the 8 bit "Arduino" can push a lot faster than that.

The advantage of the PWM DAC in isolation is that differential linearity is close to ideal and integral linearity is dependent on the quality of the reference...at 10kHz PWM clock a 3rd order Bessel filter with 1kHz cutoff puts the 10kHz component at about 1/2 of a LSB for 8 bits of resolution.

Here's a zero-drift RRIO dual for 30 cent, GBW and slew don't have to be spectacular for that:

Asymmetries (pullup/pulldown impedance, rise/fall time differences) force precision PWM frequencies down. Then the ripple filtering gets nasty. These effects pile up fast.

We use a 20-bit delta-sigma DAC that's very nice. D-S at least helps the filtering problem by pushing the noise spectrum up.

You can apply sigma-delta techniques to PWM in software, as in this old chestnut by Tim Wescott:

Incidentally here's a paper about a topology for a non-pipelined ADC that uses a reduced number of comparators, using N comparators per bit of resolution instead of 2^N - 1 like a "flash" ADC.

We've done d-s in FPGAs, to make a cheap DAC.

I have envisioned some uses for fast ADCs that are trashed by pipeline delay. The old flash parts had very little of that.

We have an ADC in a DPLL, with 6 clocks "minimum" delay specified, that constrains loop dynamics.

This is about the simplest and plausibly fastest 4 bitter I've seen, though the topology quickly becomes impossible for many more bits than that. The "comparators" can just be Schmitt trigger inverters or ECL, maybe

True. They did have a disappointing amount of aperture uncertainty though, on account of the big long voltage divider string, which led to quite different drive impedances being seen by the inverting inputs of the various comparators.

Still, a good T/H in front basically fixes that.

Doesn't need 64k individual comparators though!

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs 
Principal Consultant 
ElectroOptical Innovations LLC / Hobbs ElectroOptics 
Optics, Electro-optics, Photonics, Analog Electronics 
Briarcliff Manor NY 10510 

http://electrooptical.net 
http://hobbs-eo.com

Thanks piglet. That first Woodward article is not the one talked about in the x-chap. Though it does still use the AC trick...

I find it surprising how good the circuit is.

George H.