Digital Frequency Comparator

Homework ?:-)

...Jim Thompson

Doesn't matter, although people get Brownie points for admitting it up front. But this guy claims it's his first post, so he doesn't know the rules.

If you think it's homework, give hints on how to approach the problem, not copiable solutions.

It's digital, so I am excused. (;-)

Me too, though I seem to do a lot of non-uC stuff ;-)

I'm not sure how to do it with J-K, but the OP could use my phase-frequency detector to route the signal (see website).

But I doubt there's any such thing as an instant switch-over... it'll take a few cycles to discern the upper frequency.

...Jim Thompson

If the signals are really clean a three-state phase detector (which is, I assume, what you're talking about) will detect the change in frequency as soon as the phase rotates through one full cycle.

You _could_ do it with J-K flip-flops if you clocked them externally, way faster than your incoming signals, I suppose.

You could also do it with one 7476, if you ignored the J, K and clock inputs and just used the set and reset pins -- but that would be cheating :).

If you look at the insides of a 4046 phase detector, you will get a clue.

Tam

Or...

...Jim Thompson

And a major headache if f1 = f2. But that's life.

Have fun

Stanislaw Slack user from Ulladulla.

First off I can assure you that this is not a homework assignment, if this had come up while I was in school I probably would have been able to figure it out. But that was a while ago and it is not exactly like riding a bike...

My problem lies in the fact that I have two distinct frequencies from two different sources. Phase becomes a non-issue with different frequencies. They could range anywhere from 0 - 6.5kHz. I need to be able to determine the faster of the two without a processor, and effectively block the slower frequency while allowing the faster to carry through to the main processor. If frequency A is the fastest for

Jim Thomps> >

Just an idea. Feed the two trains of pulses to two equal one shots producing logic level outputs shorter than your fastest signal. Rectify the outputs on small capacitors with decay resistor and feed them to analog amplifier. Depending what the diff in voltages is the output can control gates to pass the relevant train. The "not an option" not tested!!! The other possibility, which you excluded, if to build a logic "processor" to compare frequencies against some internal clock and control those gates from the result.

Have fun

Stanislaw Slack user from Ulladulla.

One of the phase detectors in the 4046 is frequency sensitive. I have run it open loop with two different frequencies going in.

Tam

Hello Tim,

Or do it the brute force way. Run two fast counters and have each clock the time elapsing between consecutive rising edges, then latch these two values. Run the output of the two latches into a magnitude comparator and have that throw a (digital) mux onto the clock that had the lowest count. The system must be able to handle runts or it would need some nifty "transition extender".

Hello John,

Nah, us analog guys have to come up with an analog answer here. Like running each clock into an integrate&hold that is sampled at hold and then reset. Follow that with an LM339 and a gate or mux that selects the right clock. Then hollow out a big old digital chip from underneath, one where nobody recognizes the part number anymore, glue it all in there, connect to some pins, solder onto a board and declare it "digilog" :-)))

I think you're deluding yourself if you think it can be done without being off by ±1 count.

However this might come close...

PRECISION F-to-V converter for each input

OpAmp structure selects highest voltage (trivial)

Pipe this highest voltage to a PRECISION V-to-F

...Jim Thompson

I think it could be done with digital logic running at a few MHz clock rate, though at the cost of aligning the output to a clock period and then delaying it by a a period or two. One would measure each frequency and then determine if any given input pulse is faster than the frequency of the other chanel, gating it through (delayed a resampling clock period or two) if it is. How each frequency determining engine should be filtered against jitter is an interesting question. And of course the output will have outrageous jitter everytime it switches the selected chanel, since the phases don't match.

Maybe it's time to ask about the application?

Thanks for all the input today. I believe the quick and easy solution to my problem would be to run the two signals through a pair of F to V converters. The resulting voltages could then be run through a voltage comparator, the output of which could drive a transistor to allow the faster original signal through to the microprocessor. If the signals switched and #2 was faster than #1, the other transistor take over and signal #2 would become the new clocking input to our pic.

Thanks again to Jim Thompson for the winning entry!

Regards golfnut

cs snipped-for-privacy@hotmail.com wrote:

Aren't those going to lag the frequency by a bit? How is this going to work if you can't miss even one pulse?

In message , dated Thu, 10 Aug 2006, golfnut writes

Frequency to voltage converter on each signal, and 2-input comparator fed from the converter outputs. Three chips. Maybe 3/4 of one if you used two sections of a quad comparator to make your own F-V converters.

I think that's possible, but I haven't worked out exactly how; you basically need to make a monostable triggered by the incoming signal. Pulse-counter technique; RC integrating the output of the mono gives you a voltage proportional to repetition rate.

Keep in mind a wide-range F-to-V converter will either have an adequate integrating output-filter and be very slow, which has been stated to be unacceptable, or it will have a high ripple voltage, especially at low frequencies, defeating your ability to accurately determine the relative frequencies.

If a quasi-analog approach is desired, I suggest a pair of cycle- by-cycle period-measuring integrators, each with a sample-hold to grab the value just before each cycle's reset, and a comparator. This could be made to work over a say 500:1 frequency range, and could make a new accurate decision for each one of two cycles.

I think a circuit very like that is exactly what is needed. He needs some sort of that counts up for signal A and down for signal B.

You want to detect that you got two edges on A before the next one on B.

It could take many cycles. If the frequencies differ only a little, the circuit has to wait till the phase slides around till there are two edges of one in one cycle of the other.