PWM in a digital control loop

That depends entirely on the characteristics of your load and feedback. Do a quick model of the system and check to see if it is linear (obviously you have to linearize your PWM before you do the check). If it is, then you don't have to change your gain.

Rule of thumb -- no. Anticipate -- yes. It all depends on your application, though -- you'll need to take that model of the system again, and see if the output is too grainy for your needs.

At the cost of more ripple, you can also implement a sigma-delta modulator on your PWM. This is something that I have had to do time and time again when controlling motors, generally with good results. See

You may be able to reduce the granularity by software interpolation. i.e. produce an interrupt after each PWM cycle, and adjust the PWM output between two adjacent values. You could have PWM output 2, 2, 3,

Of course, the PWM must be fast enough compared to the process reaction speed to make this worthwile.

By linearize the PWM, do you mean the level should be considered to be the logarithm of the duty cycle?

I read that a couple of days ago. It was very informative.

-- John

If you're doing the modeling in mathmagic land I just mean taking the average duty cycle as the number.

You seem to be caught up in logarithmic relationships here, where PWM-powered things are generally quite linear. I'm wondering why. In most PWM applications you can take the PWM to be a linear stage, where the output is just the average of the PWM, which means the duty cycle -- so if you command a 1% duty cycle the effective output is 0.01 times your voltage, a 99% duty cycle gives an effective output of 0.99 times your voltage, etc.

I would like it to be able to work over a wide dynamic range, maybe

-- John

Hello John,

In case granularity at low set points remains a concern you might consider a 2nd PWM. This would become your "vernier" PWM. You can do a current summing into the main PWM output. The max current average from that 2nd PWM would correspond to the min current average of your 1st PWM when it is set to minimum. If you go all out and provide another 16bit as the 2nd PWM that should give you a granularity down to noise level :-)

Of course, you need to have access to an uncommitted CCR to do that.

My solution to a similar problem 10 years ago was to switch between two consecutive pulse widths every few cycles - say, if every 10 cycles you do PW=100 nine times and once 99, or 8 times 100 and twice 99 etc., this will give you 10 times the resolution. Somewhat more ripple but not that much as the values differ only by 1 clock cycle. I used it successfully in a HV supply (200V - 5kV), most PWM values EEPROM-able, using a HC11 @ 2MHz (its PWM granularity is 0.5 uS). It worked (still does, actually :-) at frequencies between 1 kHz and

Dimiter

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Joerg wrote:

There's a much easier way than messing around with look-up tables. See the code in

I never used a lookup table for that. You can perhaps view the technique like yielding what a sigma-delta would, however being forced to do it at the minimum possible ripple point at any moment. It just does what a sigma-delta would do if performing ideally for that application, and is actually simpler to implement than a complete sigma-delta convertor. Perhaps I should describe in some more detail the technique, I thought I had reinvented the obvious when I did it back then, but there you go, may be I have not.

Dimiter

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Tim Wescott wrote:

In article , Joerg wrote: [... PWM ...]

You can also change the frequency of the PWM to get a fine trim too. The output is N/M if N is small one bit on it is a largish effect but since M is a large value one bit on it has a small effect.

Hello Ken,

That's another nice option. You could, for example, let the end of the timer cycle run into an ISR and the ISR could add fine steps at the granularity of one processor clock cycle. Of course, the ISR itself would need a very rigid timing certainty or it would have to be "prepared" by having a 2nd compare register initiate the ISR so it's ready when the end point of the counter cometh.

If a frequency change isn't desired the OP could do this same trick with the PWM capture register output, running it into an ISR instead of initiating an instant port pin switching.