PWM Demodulation (actual SED content)

Are you trying to do anything real, or is this an intellectual exercise?

Assuming you know the frequency before hand your cap charge/discharge thingy, or any comb filter, would work. If you really wanted something that would be wholly arbitrary you could charge one cap on the + part and another on the -, then use (a - b) / (a + b). This has all sorts of practical difficulties, but those would go away after about three beers.

Yes.

Ultimately it relates to my induction heater, where I have to know phase, and phase detectors usually output PWM, so I have to PWdeM to demod the phase. Since I control output by controlling frequency to the resonant tank, and the resonant frequency will be different for different coils and loading, I need a circuit with reasonable bandwidth, say 10-50kHz.

But there are a mess of other PWM applications too, so it wouldn't hurt to know a solution to this problem.

Yeah that's kind of what I'm getting at with my first solution.. but I can't imagine linear circuits taking kindly to the exponential range needed to divide by most any number. It would have to be tuned for a specific band, which is workable for some applications, but not for others.

Tim

Just lowpass filter it, with an optimum filter. You can't do any better if you want a continuous-time output.

John

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Oh. My first answer was going to be "an integrator". You'd have ripple, which would be a trade-off between frequency and response time.

But you don't like time constants. OK. :-) Find the fastest micro you can with two separate timer capture inputs, and count microseconds. Scale the two answers (time high & time low), maybe divide to get duty cycle, and output the answer through a DAC.

Good Luck! Rich

Oh...did I mention, PICs can FOAD? ;-)

Tim

-- Deep Fryer: a very philos>

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Measure the length of the on period with your ramp - sample and hold idea, Then do the same for the off period BUT use a current inversly proportional to the voltage generated from the on pulse. You shld then have a voltage wich is a function of on/off time but hopefully independant of the period.

Colin =^.^=

"Tim Williams" a écrit dans le message de news:jpvHg.163$ snipped-for-privacy@newsfe03.lga...

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It would help to understand that a PWM signal is nothing else but a sampled signal (with sample height encoded as the pulse width instead of pulse height). Hence, all the limitations which applies to sampled signal applies to PWM signals. IE, your signal BW is at most half your PWM frequency.

A reasonably steep LPF slightly bellow 1/2 the PWM frequency will recover

Your PWM frequency is changing? Make your LPF cutoff below half the lowest PWM frequency.

On Fri, 25 Aug 2006 16:05:40 -0500, Tim Williams top-posted

I said, "micro", as in "microprocessor(microcomputer)." I didn't say anything about a "PIC". ;-)

Cheers! Rich

"Fred Bartoli" wrote in message news:44ef6e48$0$4840$ snipped-for-privacy@news.free.fr...

Yeah, but the dynamic range of my application could go from 5 to 50kHz, and things can happen faster than 2.5kHz cutoff when operating at 50kHz.

What kind of phase shift or delay would such a filter produce, anyway?

Tim

Plus some distortion. If the sampling is uniform, you'll get harmonic and combinational distortion. With natural sampling, you will only have combinational distortion.

As it literally measures pulse width (length) it truly is PWM demodulation. Frequency changes are a separate issue.

Frequency to voltage converters are simple, it had been reduced to a single IC by the early 1970's. Using the output of the F-V converter to modulate the integrator current in the PWM demodulator is trivial.

At this point you may want to use transconductance amplifiers (using the F-V signal) to modulate the corner frequency of the LPF.

So use a tracking filter -- but then the max rate at which frequency can change becomes a relevant parameter.

You could recover frequency by producing pulses on rising edges, make this a squarewave with a /2 (flipflop), control a clock oscillator with that, a divide-by-100 and a PLL, and use a switched-capacitor filter as National LMF100. The divide-by-100 is because the center or corner freq of the filter is 1/50 of the clock frequency. With this scheme your filter would self- tune to be optimal for the frequency at the moment. The max expected frequency slewrate will determine the required PLL bandwidth.

A tracking filter or cycle-by-cycle PWM demodulator could also be realized with a single DSP chip of course, but then you'd need the skill, software and equipment to write and debug DSP software and "burn" a DSP chip.

Depends on the filter type -- Butterworth, Bessel, etc etc. Also depends on the order of the filter -- so acceptable ripple in the output is another relevant parameter.