Improve PWM outputs with S/H?

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It can make sense to switch the output more frequently. Sigma-delta modulat ion exploits this.

A primitive version of this compares the desired output (a fixed 10-bit bin ary number) with a counter hooked up backwards, so the least significant bi t of the counter (which is toggling more or less non-stop) is compared with the most significant bit of the fixed number.

I thought this up around 1976, and got to use it around 1993. It's publishe d here

Sloman A.W., Buggs P., Molloy J., and Stewart D. ?A microcontroller

-based driver to stabilise the temperature of an optical stage to 1mK in th e range 4C to 38C, using a Peltier heat pump and a thermistor sensor? ? Measurement Science and Technology, 7 1653-64 (1996)

in section 2.6.

high, and DOWN while low, dithering around the intended value, in addition to slowly (exponentially) decaying to a new average output value when a ch ange is made.

So use a multipole filter, set up for maximally rapid settling.

Perhaps.

Never heard of one. Sigma-delta D/A converters are commercially available a nd have been for many years. No doubt somebody here will tell you what's cu rrently favoured. Ten bits isn't exactly difficult.

I don't know. How about some algorithm that doesn't just add or subtract bits from the end, but takes them out of the middle... in some judisious manner such that the short term average is about equal to the long term average.

George H.

The price for a S/H chip and amplifier would be a lot higher than a microcontroller with the needed DAC

Cheers

Klaus

Also, for a PWM output the VDD ripple ruins the accuracy, so a 10bit DAC on a 3V supply would need to have a supply with quite accurate voltage void of supply load regulation effects

Cheers

Klaus

Sigma-delta, in other words.

cycle

i think you will find that adding poles (i.e. more RC sections) to your filter will be easier and more fruitful.

Maybe, I don't really know about sigma-delta (S-D) DAC's. (Reading in AoE... ) Well I was picturing something different, but maybe the output pulse stream is the same. If the output was (say) 3/4 full scale what would the S-D output stream look like. I'm seeing 3 high, 1 low, 3 high, 1 low...etc.

George H.

Or if a full sigma-delta is not worth the bother, just reverse the bits in the counter value (assuming it counts from 0 to (2^N)-1 ) before comparing with the duty cycle value, as Bill suggested. Bit-reversing in software is messy, so if I'm not short of memory then I pre-compute them and use a lookup table.

When I am doing software PWM like that, usually it is to dither between two adjacent duty cycle values in a hardware PWM unit, because I ran out of resolution.

critto:

Bye Jack

Many microcontrollers have bit-reverse instructions. If you are lucky, your compiler (possibly with particular headers) has a convenient function for it. If not, then a line of inline assembly will do the job.

That's not clear. One kind of S/H chip is just a Miller capacitor (built into all compensated op amps) and a way to strobe the bias current that drives it. It's not a hard circuit to build (about the same as a programmable-bias op amp) and many PWM outputs need a buffer amplifier anyhow.

Analog function in the S/H, digital function in the microcontroller, seems like a good inexpensive pairing. An ADC on the controller adds precision resistors, and an external ADC is likewise usually a mixed digital/analog function (or takes LOTS of wires out of the controller to connect it).

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bit reversing mean you have to run at the full clock rate not the period li ke with a timer.

a sigma-delta is just a couple of adds it's hardly any worse than having to lookups and compares

Interesting: a Bresenham algorithm could make an output-only control, with fine clock timingl, that would beat the simple PWM algorithm (that only allows two transitions repeated in each fixed timeframe). That would be a hard-ish logic problem, but supportable in the right logic hardware (or could be faked up in software, given enough CPU cycles).

It simplifies the output filtering, because it isn't a 1024-clocks ripple frequency bandwidth any more. I'm dubious that it'll be the low-cost option on an Arduino any time soon, though.

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If you only reverse the higher order bits, as I did in 1996, you can run at a lower fraction of the full clock rate, and get most of the advantage.

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at a lower fraction of the full clock rate, and get most of the advantage.

what I mean is that if you use regular PWM on a CPU you'd just setup a time r and don't have to do anything until you decide to change the duty cycle

if you want to reverse bits you there is not hardware to do the work, you have to do a compare for every clock cycle

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And what I meant was that if you only reverse a few of the high order bits, you can still set up a timer.

In my 1996 paper, we did the bit comparison in a small programmable logic d evice - ICT7024 - and limited the maximum switch rate to about 280kHz (thou gh the underlying clock rate was 17.82MHz). If we'd wanted to do it in a CP U we'd have set the timer to interrupt every 3.6usec, not at 17.82MHz.

We limited the maximum switching rate because we wanted to hold down the sw itching losses in the MOSFET drivers to about the same level as the resisti ve losses - we didn't have the space to heat-sink the MOSFETs to any great extent.

I did a four-channel 8-bit Bresenham PWM in an MC68HC11 in 1999. It would be trivial in an AVR. Here's the assembly code from the PWM timer interrupt handler for a two-channel version that controlled the drive and steering motors of a robot car. Basically you just add the 8-bit drive level to an 8-bit accumulator and output the carry bit as PWM, it's completely trivial. I recall this method was called "SmoothPWM" at the time, but I can't find a record of it now.

• Motor Interrupt: CarMotorRun: ldab CarDirection ; Motor Enable/Dir value into reg B

ldaa CarSpeed ; Get main motor speed adda CarSpeedPwm ; Calculate new pulse into carry flag staa CarSpeedPwm ; and save the remainder bcs DoMainPulse ; If we don't want a pulse... andb #$F3 ; clear main motor bits DoMainPulse:

ldaa CarSteer ; Get steering motor power adda CarSteerPwm ; Calculate new pulse into carry flag staa CarSteerPwm ; and save the remainder bcs DoSteerPulse ; We need a pulse, so leave it in A andb #$FC DoSteerPulse:

• Real output: stab PORTC

• Diagnostic putchar - show the byte for PortC

• tstb

• beq CarDone

• jsr putchar

CarDone: rts

Thing is, the gain is illusory. Yes, when the signal is static, you get rid of the ripple -- for DC signals, it's a win. But as soon as the signal changes, you get a whopping huge step, or staircase, as the filter follows the change, and the S&H chops it up.

It's just sampling theory all over again: the S&H is a first-order hold. We can apply this theory to see that, we haven't filtered anything, we've just sampled it, putting F_ripple at Fs, where the ripple gets aliased to DC.

Indeed, if we vary the phase between PWM and sample clocks, the output DC offset varies, as it's intercepting a different point along the ripple waveform. How do you know what phase is correct? Are you going to calibrate it?

Any ripple that appears within the sampler's bandwidth (i.e., Fs/2 give or take) is passed unchanged, or indeed may be worsened because it's squared up in the process -- you get THD, that still needs to be filtered if you want a smoothly changing signal.

So you still need the ripple filter. You've aliased F_ripple to DC, and aliased everything else to the harmonics of Fs.

You can solve some of this in digital -- in which case the solution approaches a S-D converter of some order. Or solving it in analog, it's just a higher order filter with the usual bandwidth and settling time tradeoffs.

No free lunch. ;-)

Note that higher order S-D converters have a multi-pole filtering effect. They call it noise shaping. The effect is to reduce converter noise in the passband, pushing it up closer to Fclk. You get wider bandwidth for a given SNR.

Tim

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