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I2C "SCL" line problem

Hi all,

I faced the following problem with my I2C slave code(VHDL).

I was incrementing a counter on the negative edge of SCL(this clock is coming from the processor's I2C port , 100 KHz frequency). But what i observed on the CRO was that my bit counter which was running on the "negative edge" of SCL , was incrementing on "positive edge" also and this was not happening always.

The solution to this problem was i inverted the incomimg clock "SCL" and used the rising edge to increment my counter now it was fine.

Can any I2C experts clarify what is the problem with working on "negative edge of "SCL" clock.

Regards, Prav

Reply to
praveen.kantharajapura
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What I suspect is that the rise time of the SCL is too long for your counter, so the input stage briefly oscillates. The rise time of the SCL (an open-drain signal) is always pretty long since it depends on line capacitance and the pull-up resistor. The falling egde is pretty steep since it is actively driven low.

The solution would be to either lower the pull-up to meet the required risetime, but there are limits on the value, dictated by the I2C standard. So a better approax is to add a schmitt-trigger to make the rising edge steeper so it does not trigger the counter. When you added an inverter, this probably also helped shortening the risetime.

Meindert

Reply to
Meindert Sprang

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