Got a client where we will eventually need to pour our stuff into an ASIC. Mostly analog along with some serial port glue logic. Afraid that Jim isn't with us anymore so how does one find a preferably local ASIC design services provider in the greater Sacramento area, California? Someone who sees it through from the design to production.
All the lists I have seen aren't very useful because they do not allow listing by location.
I've written to TSI in Roseville but that's more of a fab than a design house. If not local it would have to be someone in good reach of a local airport or maybe along Interstate 5.
I've had good results farming out PCB design, non-local. A good communicator is important. It can be hard to communicate more than three or four time zones away. However, I'm an early riser, and have found working with a late riser in Europe leaves a pretty good cross section.
Another alternate is, write a well-thought-out, really good spec. Then you can live with a 12-hour mis-match.
Not many details yet but it'll be in the several thousand devices/month. Right now we are just looking if there are any resources available without a lot of travel.
Yeah, mine always required a flight so far. However, that was because we needed top-notch analog chip design skills at the design house. That meant Southern California, Arizona, and so on. I get TSA-pre at the airports but it's still a major time consumer to have to fly there.
Not so much for this one. Compared to the chips I was involved in so far this is almost plain-vanilla.
Of the two designers I like, one is most likely no longer among us and the other took a job at a major semiconductor manufacturer so is no longer available.
Thank you. San Jose is about 3h drive each way depending on traffic. Occassionally 5h but ... no flight required. Unless I had a pilot license and a Cessna at our village airstrip.
We also have an Amtrak train connection to San Jose.
Same here. Have to because my local layouter had some health issues come up and retire. Though even him I never visited over about 20 years. Got to do that one of these days just for a coffee and visit, may be by bicycle.
My favorite online conferencing service is currently Zoom. Yesterday the audio fell apart for the first time which is a serious problem with many other services but in this case it was because the client uses WiFi.
Advice to novice readers: Do not use WiFi for online conferencing. Make sure it's good old CAT-5. If you can't have that for whatever reason establish an audio link via telephone. POTS preferred, as VoIP in large corporations can have its issues. Always have a cell phone with good hands-free performance available in the room, in case everything goes to pots.
That's exactly what I am hammering in at my clients. The spec is paramount.
For time zones, my current PCB layouter is 3h away in time zones and that's ok. 9h-12h can be a pain because of the usual 1-day delay in question-answer. Also because online face time and cooperative design requires family disruption on at least one side, with Asia usually on both side.
Not many details yet but it'll be in the several thousand devices/month. Right now we are just looking if there are any resources available without a lot of travel. "
Next question is whether size is an issue. For low to mid volume, multi-ch ips module might be more cost effective than all custom single chip, especi ally when mixed signal is involved.
We can probably hook you up with the right people, since we are just couple of Amtrak away. By the way, my last fame war with JT was cost. I would n ot get involve with less than 100k $, but he would handle less than 50k. H e might have been able to do it cheaper, but I outlive him.
I like to be really close to the person doing the layout, preferably just down the hall, so we can discuss things on the spot. It's very interactive. My mechanical designer stays close to the layout too. He worries about packaging, connector placement, manufacturability, things like that.
I also like to do some critical placement and routing myself as the design progresses. That's important for fast stuff and for thermal and packaging issues. Luckily we have enough work to keep an in-house guy busy.
My engineers and I like to do an entire board ourselves now and then to keep in practice. Small ones and prototypes mostly. I think engineers should really understand the process.
It's really hard to document all the issues, for an outside guy, enough to cover all the things that matter. Some of it you just push around until it feels right.
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John Larkin Highland Technology, Inc
lunatic fringe electronics
You might get in touch with Jon (forget his last name but he's often seen here). He sells & manufactures numerous circuit boards and he's also conected with a local university that has made use of some of the wafer sharing firms. You might check the archive for this newsgroup and the metalwork (?) group.
I think a regular chip would be best. This stuff doesn't require a specialty process. Regular CMOS or BiCMOS wold suffice.
If your company offers IC design services and turn-key project handling can you shoot me an email? This client is seriously interested. Not something that will happen tomorrow but it likely will this summer.
The address in my news post headers is valid. Though theoretically a glitch could happen during a few hours in the next week because I started switching hosts for my web site.
Consultants have less overhead so they can be very competitive. However, there aren't enough of them to go around, just like in my field of analog circuit design.
Yes, for fast or noise critical stuff. Though I never had problems doing that remotely.
They should but they are too expensive to do layout. Also, good layouters stay abreast of the latest developments in production technology, something an engineer just doesn't have the time for.
True. Though the guys I am using have a good enough EE background that I don't need to explain SMPS intricacies and pitfalls in too much detail. One paragraph with a sketch is usually enough.
Jonathan Kirwan? I haven't seen posts from him in more than a year. We'd like to use a commercial outfit, not via a university (where this client already has connections).
The spec has to be almost waterproof. It actaully becomes part of the contract. Changes at a later date result in change orders and that can easily blow apart a budget.
I remember when a client used my proposal (!) as a spec and it became part of the contract. I had to suppress a sentence that couldn't be printed here when I found out. It all worked out well but everyone wiped sweat off their foreheads afterwards.
On very tough chips with lots of compromises to be discussed it can be a problem. Not insurmountable but I had to fly several times during IC designs. Having the team in driving distance would be nice, especially when you have to visit with a team. Train access at both ends is nice as well but that's a sore point in the US. They sometimes give the more lucrative freight trains priority and then you are late. It's not like the bullet trains in Europe.
Joerg: not Kirwan, though that does sound familar. tis Jon Elson at snipped-for-privacy@picosystems.com. He had some mesages on this group that involved the firms that organized the sharing of a wafer. Maybe an archive search?
I'll contact him though a shuttle run isn't what we had in mind. Shuttle runs can be helpful for trying something without a huge foundry bill and (usually) if not in a hurry.
This sounds like me. Well, I do NOT do IC design, that's just a level of detail that is too much for me. We have a guy at a neighboring university that puts his Master's candidates to work on various mixed signal designs we need. He is great, and the students he selects for this are really good, too. Several of them have then come over to our university for Doctoral programs (his U doesn't go past masters.)
But, this is not an IC design house, and with grad students, things will go very slowly. Also, as a commercial product, we CANNOT get involved in it! Our Cadence license specifically prohibits any commercial use of the designs we work on.
MOSIS used to be a great resource for getting chips fabbed, but they are becoming more and more difficult to work with. They no longer have the old AMI C5 process (now ON semi) available, we are doing a chip now through them at AMS (Austria MicroSystems) but MOSIS will not have that process after this summer. Looks like a really great process, but the fab is going all in-house on sensor technology, the Fraunhofer institute is trying to move the process to another fab. Likely a 3-year outage before they get it running well again.
So, the availability of these multi-wafer runs is getting harder to find, too. And, the cost of a mask set even for low-density chips is insane, several hundred K USD. So, you have to be looking at pretty high volume before dedicated wafer runs make sense. Then, you have to deal with packaging and testing of the die, too. Several thousand chips/mo is starting to get to where it may make sense, especially if the product will have a long production life.
There are so many super-compact (chip-scale) IC packages now available that it makes a lot less sense to go the IC route for mixed signal stuff. You can pack a lot of analog functions onto a square inch of board.
The stuff we are doing is in the 100K transistor/ die range, and would be pretty hard to get more discrete technology to fit in even 4 X the space.
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