ASIC design party

Apr 21, 2019 4 Replies

We wanted to party, but nobody is ready yet. So, the party is rescheduled to June, July or Aug. Meanwhile, we can start working on the tools.



JT took back all his designs to his grave. So, we don't want that to happen again. Everybody should be able to fix/modify the design, Currently on Linux only, will provide window version when ready.



Working on shift register to select channels. Example of a 4 channel decoder:



The layout is all done with commands such as:



SPAD C2 # create solder pad at row C col 2 NAND D1 # create nand gate with x = !(a*b) INV6 E1 # create two inverters (bit 2 and 1) D1y->E1c # wire 2nd output to 3rd input



shell> asic decode Create decode.sdg from spec file decode.asic



shell> sdg decode Create decode.sdg, decode.lst from input file decode.sdg



Details at http://75.101.56.77/asic


Very interesting indeed

I cannot see which tools you are referring to?

Been searching previously, but never found a freeware tool and specifically not a tool that would be able to use libraries from Cadence

Regards Klaus

ly not a tool that would be able to use libraries from Cadence

It's some tools we developed to penalize layouts. Ir does not attempt to d o a complete routing, but rely on a matching PCB (0.2mmT pitch) to finish r outing (the large orange pads).

The images are using

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The GDS3D UI is very simple. too simple. It would be useful to be able to specify the viewport from command line. and to select layers. Fixing up GD S3D would be one thing to do, after the ASIC compiler itself. The compiler should also output the matching gerber files for the PCB.

:

ally not a tool that would be able to use libraries from Cadence

do a complete routing, but rely on a matching PCB (0.2mmT pitch) to finish routing (the large orange pads).

create panelized layouts.

o specify the viewport from command line. and to select layers. Fixing up GDS3D would be one thing to do, after the ASIC compiler itself. The compil er should also output the matching gerber files for the PCB.

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