How do display adapters share memory

Jan 31, 2005 2 Replies

Hi,



here's something I've been pondering for some time. How does the RAMDAC (correct term?) and the interface to the display adapter share the display memory? The RAMDAC has to have a constant access to the RAM so that it can keep feeding data to the display. So when does the actual adapter get its turn?



So far I've figured out following possible solutions:


- The interface caches accesses to the display memory that occurr during a horizontal display line and unloads to the actual display memory during horizontal and vertical blanking. Would need flow control.



- The interface allows accesses only during vertical and horizontal blanking. This doesn't seem too smart, since the other end needs to wait for blanking.



- Some kind of double buffering scheme. Part of the display memory that should be displayed gets copied during vertical blanking to a separate memory that is dedicated for the RAMDAC. This doesn't make sense though since I remember seeing a tearing effect on older PCs displaying realtime graphics without double buffering in the software.



- Double port RAM. This is quite expensive isn't it? I dug up some old display adapters and the seem to have DRAM in them.



I'd appreciate, if someone could tell me how the trick is done :)


Juha Turunen (turunen(at)iki.fi) elpuri@IRC | The problem with the global Torikatu 5A4, 53900 Lappeenranta, Finland | village are all the global GSM: 040-7092525, http://iki.fi/turunen/ | village idiots.

It depends. Some PCs (which I think the OP was on about) the system memory is shared , with some of it going to the video adaptor. This is simply a very high priority read of main memory, with maybe a 1K buffer on the RAMDAC. There is no dual port RAM.;

ISTR that (in the early IBM interface cards) the CPU had priority access of the RAM, so any video access that happened at the same time read the location as zero, and for that scan showed a dark spot on the screen. There was a hardware-driven bit on the card that was active during the video scan and went inactive during retrace, so the program could read this bit to wait to access the video RAM during retrace and thus not disturb the display.

Yet another way is the Apple ][ design. For one phase (half-cycle of the CPU clock) the video display reads a word, and for the other phase the CPU does its memory access (read or write) cycle.

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