The TL08{1,2,4} datasheet lists no input current spec, and only has this to say:
"The magnitude of the input voltage must never exceed the magnitude of the supply voltage or 15V, whichever is less."
I would have expected to find a max input current spec of 10-20mA or something.
Is there some reason why the JFET input amp cannot tolerate ANY input current?
I was hoping to use a resistor, to a bipolar clamp to ground, preceding another resistor to the opamp input for protection. But if they are to be taken seriously, then this wouldn't protect in the absence of power, because current would flow. Thus, I may have to go back to the clamp to rails approach, which forces me out of the cheap TL082 to something else that can tolerate slightly more input voltage than 15V (in other words, specified input current max).
Don't ya' just love datasheets!
Thanks for comments.
Good day!
--
_______________________________________________________________________
Christopher R. Carlen
Principal Laser/Optical Technologist
Sandia National Laboratories CA USA
crcarle@sandia.gov -- NOTE: Remove "BOGUS" from email address to reply.
No, that's not what I mean. I am talking about what happens when the input *does* go outside the rails. In that case, I want to ensure the little thing doesn't get broken.
Most devices have maximum input current specs that allow you to figure a resistor value to protect the input from overvoltage, by limiting the current to a tolerable level.
The datasheet for this JFET input amp doesn't tell us much about whether the inputs have built-in protection diodes to the rails or not, or if voltages greater than the rails would result in the JFET junctions turning on.
Perhaps for this device even miniscule JFET gate current would compromise specifications or something, which may be why they are so strict about the input voltages, while not specifying an input current.
Good day!
--
_____________________
Christopher R. Carlen
crobc@sbcglobal.net
SuSE 9.1 Linux 2.6.5
An ideal op-amp has infinite input impedance, therfore the current flowing into an input would be 0 regardless of the voltage present. Obviously this is the real world and the input impedance is "much" lower, you should expect several uA of input current to flow. Just don't present a voltage to an input that is outside the supply rails.
The National Semi datasheet is prolix on the topic :
"These devices are op amps with an internally trimmed input offset voltage and JFET input devices (BI-FET II). These JFETs have large reverse breakdown voltages from gate to source and drain eliminating the need for clamps across the inputs. Therefore, large differential input voltages can easily be accommodated without a large increase in input current.
"The maximum differential input voltage is independent of the supply voltages. However, neither of the input voltages should be allowed to exceed the negative supply as this will cause large currents to flow which can result in a destroyed unit.
"Exceeding the negative common-mode limit on either input will cause a reversal of the phase to the output and force the amplifier output to the corresponding high or low state. Exceeding the negative common-mode limit on both inputs will force the amplifier output to a high state. In neither case does a latch occur since raising the input back within the common-mode range again puts the input stage and thus the amplifier in a normal operating mode.
"Exceeding the positive common-mode limit on a single input will not change the phase of the output; however, if both inputs exceed the limit, the output of the amplifier will be forced to a high state.
"The amplifiers will operate with a common-mode input voltage equal to the positive supply; however, the gain bandwidth and slew rate may be decreased in this condition.
"When the negative common-mode voltage swings to within 3V of the negative supply, an increase in input offset voltage may result
Reviewing this commentary while looking at the detailed schematic should give an understanding of why there's no "maximum input current" specified. It'll also help you figure out whether the resistor/diode clamp you're proposing will work. Although you want to thoroughly degrade the input characteristics of the jfet with the protective circuitry!
Best regards PN2222A TO-92 was good enough for Dad, it's good enough for me!
Ok, I understand why the thing should theoretically accomodate positive voltage over the positive supply.
Right. Negative voltages would turn on the JFET gates. But since this can happen easily with an unpowered device whose input is connected to powered circuitry, still why wouldn't they specify a maximum current?
Nope. Still doesn't make sense. If there is any way for current to flow into the input, then there should be a spec for max current. TI gets around this by simply warning to never allow inputs to exceed rails.
From what I gather so far, I should prevent the inputs from exceeding the rails, at least on the negative side. The positive side we expect won't draw current, but TI still insists that the input should never exceed the rails. This is their way of getting around having to quantify a breakdown voltage for the reverse biased JFETs.
I have a potentially bipolar input that I want to rate to tolerate up to
+/-30V, with the power on or off. So it will have to be clamped to within the the rails, even when the rails are zero. If the power is off, that is impossible. At best I could ensure the inputs to be less than about 0.6V of the rails, which could allow partial turn-on of internal JFET junctions. Thus, a strict interpretation of the specs would indicate that it is impossible to protect this device from external inputs when the power is off.
A more liberal interpretation might allow for some gentle input current if the input goes negative with power off, but a limiting resistor is used. But one cannot compute this resistor without a max input current spec.
Yes, of course!
And what's wrong with 6C4? ;-)
Thanks for the input.
Good day!
--
_______________________________________________________________________
Christopher R. Carlen
Principal Laser/Optical Technologist
Sandia National Laboratories CA USA
crcarle@sandia.gov -- NOTE: Remove "BOGUS" from email address to reply.
Yeah, maybe I'll give that a shot, after I figure out a bunch of other troubles with my Linux permanent-headache.
Now that's a perfectly respectable thing to do! I have been proposing a switch to all tube front ends around here since I started. Can't beat 'em for ESD and fault tolerance. :-D
No more trips
--
_______________________________________________________________________
Christopher R. Carlen
Principal Laser/Optical Technologist
Sandia National Laboratories CA USA
crcarle@sandia.gov -- NOTE: Remove "BOGUS" from email address to reply.
I recall using one of these (or perhaps a relative, such as the LF353) for a 3V battery monitor. The battery was used to supply a few uA for a ram when the main power failed.
The requirement was that the battery monitor should not draw current from the battery when its own rail was at zero volts. The P-ch JFET input worked quite well for this. i.e. voltage on opamp non-inverting input = 3V. Voltage on all other opamp pins = 0V. No (measurable) current flowed; nothing was destroyed.
I did put a series resistor in there, but that was just to cover the case of the cells being inserted backwards.
Under 'Absolute Maximum Ratings' of the TI data sheet, there is a notation; "The magnitude of the input voltage must never exceed the magnitude of the supply voltage or 15V, whichever is less."
With JFet inputs, a maximum input current spec in excess of bias currents would be redundant, if absolute maximum ratings were otherwise observed.
Competing mfrs must use the same data sheet, to second-source the TI house-numbered part under license, with the same ID.
Other, similar TI circuits, such as TL087, DO specify a maximum input current of +/- 1mA, however, if you simply want a process-dependent limitation.
With a Ciss of only 2 - 4pF at -1V (where Id ~= 1mA), the BF245 appears to be a rather fragile device. Hmm, I've noticed they're pitching much higher-capacitance JFETs now for receivers.
I'd suggest to write to TI and National and ask about that. Not that it is guaranteed to result in the answer you want to hear but all it costs is a couple of emails. Both companies are very responsive.
JFETs can be rather fickle. I remember when I was young and used BF245 and others in an antenna pre-amp. With protection diodes and all. Almost after every thunderstorm they had either gone to lalaland or exhibited very degraded performance. To avoid having to climb a slippery roof all the time I finally replaced it with, ahem, a tube amp. No more trips onto the wet roof, ever. No forming of ice clumps on the amp either ;-)
In many FET type inputs, the failure is due to excessive current. However, this is not external current.
It's current flowing through a weak point in the internal capacitance of the input. Once the junction is charged up high enough, the capacitance discharges through a defect, and literally explodes part of the junction.
I thought Linux is better than Windows. But probably not as good and simple as DOS. Come to think of it, there isn't much that I can do with a 'modern' OS that I couldn't with DOS. It's the same with cars, they become ever fancier. Then something breaks and even an engineer can't fix it.
Another advantage was that the tube had a dynamic range from here to the Klondike. Huge signals left it unfazed. Also, it certainly outdid its guaranteed 10,000 hour lifetime and kept going until we had to move. Reminds me of why Bob Pease hung on to his VW Beetle.
That can be even more nasty than a total failure because the device may still 'kind of' work. I have had quite a few JFETs that were biasing ok and all but where the noise figure had become lousy. After replacement everything was fine. I guess that is why my first scope had all the JFETs in sockets.
Fragile indeed it is but a great transistor for the money, considering its age. The common drill went like this: Wrap a springy wire around the pins unless it already came with this contraption. Then pull it out of the foam, insert it, solder (unless socketed) and slowly pull the wire off while the palm of the hand touched the chassis. The solder iron had to be grounded and connected to the circuit board ground. Preferably this job should no be attempted on a dry winter day.
Even new stuff can be that sensitive. I remember a tech at a client who duplicated my prototype. There was an SD5400 array on there and it was blown. So, he exchanged it, blown again. I told him how critical it is and he double-checked all his ESD mitigation gear. Still, the third one was dead again. Now he was about ready to throw his coffee mug at me but after we did the next one together it was all fine. No problems in production whatsoever. The SD5400 is one of the most practical arrays in RF work, lots of 'wacky uses'.
IOW dT = pulse_energy/[Si volume * density * specific heat capacity]
by the time dT is say 500K then things start to go horribly wrong for poor old mr Si.
a small bit of silicon will get a lot hotter for a given pulse energy dE than a big junction will. A powerex 1200V 600A IGBT (about 1cm x 1cm x
1mm) will happily sit with 700V across the device with 6,000A of current flowing (ie 4.2MW) for 10us or so during a desat. By the time you get to about 30us though - kaboom.
By comparison a sot23 bjt is easy to fry by accidentally shorting things out with your scope probe (hangs head in shame. Si murderer...). Also depends on localisation of heating etc. aint mechanics fun :)
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