Help with high input impedance amp.

I'm assuming the schematic is drawn correctly and the transistor is an NPN. Can I use aluminum polarized 1uf capacitors? If not, what would I use. Should both caps have the positive terminal connected to the emitter of the transistor? Seems kinda close, but what happens when it starts swinging? Maybe I should I have non-polarised 1uF caps. What kind? The schematic,

There are no 1uF capacitors in that schematic. They are 0.1uF, but the decimal dot is all but vanishing. It wouldn't make much difference though. Either should work. If you really want to use polarized capacitors, the NPN emitter has the lowest DC potential of the three junctions, so the negative terminals of the caps should be connected there. For AC, the three nodes swing the same way, near enough, thanks to those two capacitors. That's what bootstraps are

That said, it's about time you Americans drop the silly .1u. Dots *do* vanish. Use 100n. This schematic breaks the point, if you'll excuse me the pun.

The schematic is otherwise correct, it's an NPN alright.

Jeroen Belleman

The BJT is a jelly bean NPN, I suspect typo for the once popular 2N3643 (I found some in my junk box even!). Use 2N3904 or 2N2222 or BC548 whatever. The BF256 you used in the first version should be a fine substitute for 2N4416 - they are both listed as process 50 parts.

Everything between your Zin input test resistance and the gate should have minimal stray capacity - i.e. built up in the air a few mm above the board.

piglet

We have success! I laid out a pcb in Paint last night and etched it this morning.

If you haven't read my previous post, IT WORKS! I used the BF256C and MPHS10. I understand the 1uF is wrong, and it should be 0.1uF. I'll be changing both. I had some internal debate, on how to place the 2.2MΩ, 1MΩ voltage divider that drives the 10MΩ gate resistor. So, I ended up running the input under the 2.2MΩ resistor, I have removed the ground plane from both sides of the pcb in that area. Thank, Mikek

Good! Congratulations.

First finish adding the bypass caps. Followers with even slightly capacitive loads can have a region with negative input resistance. Maybe you're getting close to such conditions.Try a ferrite bead in the gate lead, maybe. You may also try out what happens if you remove either or both of the bootstraps. Shortening the leads of parts, making the circuit more compact, might help too.

Jeroen Belleman

I am very pleased for you. Thanks for letting us know. My first reply mentioned bootstrapping away the drain capacity and that seems (along with minimising wiring strays) to have been one of the factors.

You might be able to get rid of the gate bias bootstrap since at your frequencies it won't be helping much?

piglet

I have added the bypass caps and changed the 1uF to 0.1uF. Also fixed the lack of ground on the input, it was soldered but I had cut the foil to that section of ground plane. grounding the input made it susceptible to a 200MHz oscillation, comes and goes depending position, if I'm reaching to adjust the sig gen and maybe how I'm holding my tongue. I"ll try the bead and if the doesn't help, I'll shorten the FET leads. After the changes it is a lot tamer, it is a very gradual rise in amplitude as frequency increase, no peak (at least to 30MHz) and only 6% from 1MHz to 30MHz.

Ok, I just added a piece of aluminum foil on the underside of the pcb to act as a ground plane That makes takes away the level rise with frequency, much better. Also no more 200MHz oscillation seen. I'll try a more permanent underside ground plane, I have some wide copper tape, I'll apply and solder.

I added a underside groundplane, it tamed the 200MHz oscillation and flattened the response. Here's a picture at ~1MHz and 30MHz, only a 2% rise at 30MHz.

This seems like a big part of the solution given how Mikek's circuit now functions (even with wrong component values) on his new PCB with a minimal groundplane. Danke,

Anyone care to look at this Chinese design for a high input impedance amp, and give me their thoughts about it? Two FETs, two transistors, a little different than I have been looking at.

Wow! This almost seems Rube Goldberg. T2 is a current source. T3 is a voltage source. The net result when combined with T1 is to produce a very high input impedance. T4 is to provide more isolation to provide a lower output impedance.

Interesting. Wait! I missed C2, which will provide positive feedback, raising the input impedance further. Yes, interesting circuit.

It is fundamentally the same as the one you did yesterday. T3 and C2 bootstrap away the FET drain capacitance, the other circuit didn't bother with the T3 follower using merely an RC. Not sure if the added complexity is worthwhile or risks more instability. Behavior with large signals may be different but at first glance can't say which is better or worse, need further thought!

In the real world performance will be dominated by physical layout strays. If you build it please let us know.

piglet

Followup #2 - both give roughly similar results - if you can afford the higher supply voltage of the simpler circuit use that, if you want to operate from 9V use the more complex circuit?

piglet

It's very similar to your previous circuit. Again there is the JFET follower T1, followed by an NPN follower T4. T2 is a current source, so that the gain of follower T1 will be very close to unity. There will be virtually no AC voltage across R2, nor across R1, multiplying the apparent resistance of the latter a lot.

C2 applies the output signal to follower T3 which bootstraps the drain of T1, reducing the effect of Cgd of that JFET.

In conclusion, it should work fine.

Jeroen Belleman

There is the rub, proper layout, on iteration 3, I followed a couple of the ideas given here, removing the ground plane and getting the parts raised above the board, although without the ground plane I don't think raising the parts mattered. I suspect removing the ground plane from the enter circuit was,

not as important as for the high impedance FET area?

I used long leads to keep the parts physically separated, but I know that leads to inductive strays, so... l 'll be reading up on how to mitigate pcb strays before my next build. If anyone has a favorite site on the subject of stray mitigation, please post.

Is there any advantage using smd components?

I thought there was, but the last build did pretty well with leaded components.

Is it worth using a pcb software program, so I could make thinner tracks to help minimize strays? >If you build it please let us know.

I did order the transistors and FETs last night, so there is a possibility, but other projects first.

I can think of only one way to test the input impedance, that is with my Q meter. Set up a LC at resonance and then add the high input impedance circuit across the tuning capacitor. Then read out the change of the tuning capacitor and how much the Q drops, then do the math on the Q change.

With the input current so low, is there another way? Thanks, Mikek

If 30MHz is your max frequency then lead length inductance of THT components is unlikely to be a big problem. Your goal of Hi-Z means low stray C and capacitance is proportional to area divided by distance. THT parts will get you distance between nodes whereas SMD parts will reduce node area. Usually SMD wins but with care you could get THT to work. Don't forget the dielectric constant of pcb substrate is 4-5 times that of air (and lossy).

The BF256 is similar to 2SK192 and none of the parts in the new circuit are special.

Didn't you say before you measured input impedance by inserting variable high resistances between input jack and FET gate and finding values that gave 3dB drop? I recall the figure 30kohm from an early post?

The Q meter method should work too and since that appears to be your end application that method might be the gold standard even though tedious?

piglet

Don't forget the dielectric constant of pcb substrate is 4-5 times that of air (and lossy).

Yes, and that is part of removing the ground plane, although it had a slight level peak at 29MHz and was up a little at 30MHz. That calmed down when I add the underside ground plane.

The thread (on an IO Group) that got me started, was asking about building a Q meter with a range of

Not, that I understand a lot about FET characteristics, but the 2SK192A has a minimally lower Crss and there is no spec for Ciss on the BF256C but the 2sk192A spec is 3.5pf, so I'm thinking it might also be a bit lower than the 256C. The Forward Transfer Admittance is higher on the 2sk192A and ! can't compare the power gain because they are measured at widely different frequencies. So, for those reasons I chose to go with the specified FET. It's either right or it's wrong and an expense I didn't need!

I did, and I think that was at 1MHz. Although later I tested again and with the 30KΩ the output was lower, I don't know if my generator was set to a higher frequency, but, I let that go until I have another amp to compare it to. I also don't know what strays I'm adding with my input series resistor. I like the Q meter, because it has a + and - 3pf tuning cap graduated in 10ths of a pf. A 0.2pf change on a high Q inductor is clearly seen, so I figure its a good way to find the input capacitance. With a with a high Q inducto,r 1250Q at 1MHz, a 50 point of Q drop is 45MΩ additional load resistance, I should easily see any drops. I'll need to setup my Q meter and verify that. Seems high, but that's what I calculate, although that does not include the losses in the gate capacitance and strays.. Thanks, Mikek

Years ago, I built this Kleijer High input impedance amp.