I laid out and etched a pcb for the this 2 FET RF amp. (MW) It has no output signal. The obvious thing to check is the layout, I think I have it correct. I set the pot, so the gate of J301 matches the gate of J271.
I have labeled measured Voltages on the schematic.
If needed, I could remove the 220 ohm and pull up the Source of the J271 with a resistor Value ( ? ) to 12V, To aid troubleshooting.
It seems to me that you have measured the voltages with a voltmeter with insufficient input impedance. The FET gates will need an instrument with gigaohms of input impedance (VTVM or a good digital multimeter).
Yeah really. The gate is at + 5.2 and the source is at 5.35. It is in compete saturation. That means the NJFET is working into the 22 ohm shunted by what has become a capacitive divider, feeding the output balun.
Set the pot so that the source of J 271 becomes at least 6.25 volts or so. Note, turn it in the direction to lower the voltage at the gate or it will mislead by raising it because of the G-D junction.
Why did you use depletion mode FETs BTW ? Low distortion maybe ?
Depending on the voltage output level desired you might need to lower the 2
20 ohm, but make sure that J 271 is not saturated anymore. This seems like a unity voltage gain amp to drive a biax or "twinlead", simply lowering/mat ching(?) impedance. You might want to put some phasing dots on the transfor mer/balun because wired as shown it won't work. It will put the same polari ty signal on each conductor, which I doubt was your intention.
I'm using a Fluke 73III, I believe it's a 10Mohm input. I'm measuring 5.2 v on the J271 gate, it would be 5.4V without the meter loading. My math says the J301 gate resistance looks like 764k ohms. That's measuring with the meter and them backing out the 10M ohm loading of the meter. Isn't that to low for a FET gate? I'm going to wash the pcb.
Maybe, but I already changed that part, without effect.
I have made plenty of stupid mistakes. In fact probably the reason my unedu cated ass knows anything is because one learns from mistakes. HA, the peopl e who make more mistakes than me do so because they DO more than me.
The OP does not have that cocky attitude. You know the type. That type I wi ll tear down like a house of cards over anything, grammar, not knowing what a frikken transformer is (remember that one ? the SMPS wall wart ? probabl y afraid to show up here after that)
But recently I had to modify something to use a silicon for a germanium tra nsistor. I figured no problem, just increase the E-B bias right ? Well what IO did DECREASED the bias. It got pointed out to me kindly, but the guy co uld have said "DUH". I made the mistake because I was unfamiliar worth usin g a negative source, singly. But that is no excuse.
Hold on. I just made a stupid mistake. The pot controls bias to the TOP FET. You need to lower the bias on the BOTTOM FET. The pot will do no good. Can you maybe just reverse the connections ?
If not, throw in another 1 meg from the bottom FET gate to ground, it should at least get some output. Then you can tweak it. The source voltages need to be comfortable or else you'll get crossmodulation, but exactly what is comfortable ?
There is one other possibility, turn the pot to increase current in the top FET, but watch the current, those little RF transistors might be pipsqueaks.
Sorry about the mistake, I'll find something to blame it on later :-)
Note the pot is controlling the voltage on the gate of the J310, indirectly controlling the voltage on th3e source of J271. I had to increase the J301 voltage to get J271 voltage up to 6.25. This didn't give my any RF output signal.
Not my design, But a well tested circuit, it is supposed to have very high intercept points. MW Band intercepts: IP2~ +88dBm, IP3~ +41dBm, -6dBm preamp gain.
Yes to drive twin lead. High impedance so it doesn't load a Flag or Delta antenna. This alone provides a 6db voltage gain over a matching system. Flags and Deltas are very low output signal antennas, (-40db).
Re the output balun, walk me thru this. I twisted 2 ft of wire, then wound the twisted pair through my toroid for 24 turns. I have one end of the twisted pair connected to my output and ground the other end is terminated with 50 ohms.
0.15 volt of forward gate bias on a jfet won't break anything, and the fet is not "saturated."
But the circuit is obviously lopsided.
Jfet Idss specs often cover a 5:1 and sometime 10:1 range. The pfet and nfet are obviously far apart here. The pot is a symptom of that Idss spread, but it actually doesn't make much sense. May as well connect the gates together.
John Larkin Highland Technology, Inc
lunatic fringe electronics
Shouldn't it be ? I guess you're right because there is voltage from S to D , but why ?
connect the gates together. "
For depletion mode ? Wouldn't that make that 220 ohm a bit too low ?
Just trying to learn here, it really seems like it should be fully conducti ng.
The only thing I ever thought of doing with a depletion mode FET is to open up the return of a global feedback network of an audio amp for clipping pr evention. Never actually tried it in practice but in that scheme it would n ormally be saturated, so that issue does interest me a bit.
The transfer curve of a jfet (drain current vs gate voltage) goes smoothly through zero volts. Positive gate voltage makes more drain current, above Idss, but the gate is a diode that will start to conduct past a few tenths of a volt forward bias. The expensive PAD1 picoamp diode is actually a jfet used as a diode.
An n-channel jfet behaves a lot like a triode tube. Needs negative bias to turn it off, works with positive bias but draws grid/gate current.
The s-s resistor could be chosen to set the standing current. But Idss variations make that a little tricky.
The p-fet will conduct close to Idss with near zero Vg-s. Both fets will run at that current, which looks to be about 10 mA.
John Larkin Highland Technology, Inc
lunatic fringe electronics
Ok, I have it working, I made a layout mistake. I gludged around that and now I have an output and it is 1/2 of the input signal. I'm thinking the -6dbm above means I should have half voltage out. Correct me if I"m wrong.
I have no information on how to set the bias except for minimum IP2, and I'm not setup for that. There is a sweet spot where gain is max when I adjust the gate bias pot. The sweet spot has 6.4V on the gate and 8.6V on the Source of J310 and 5.2 on the gate and 5.6 on the source of J271. I'm settling for a compromise where the source of J310 is 0.9V above
1/2 B+ and The source of J271 is 0.9V below 1/2 of B+. Until someone tells me different.