gated pulse stream problem

You fall in the "it's possible" camp, then. But you use a shift register instead of a flip-flop? It looks like the gate AND will be turned on one clock pulse after the select signal goes high, but then turn off again after 7 pulses, no matter if the select signal stays high or not (as soon as the input signal is shifted down to QH)?

Yes, thank you for the schematic. I need 1 to maybe 1024 pulses per burst, selectable through adjustment of the width of the gate.

So you want pulses as long as your "command" is high, just not truncate on either end?

Is that correct?

My original reading was that you wanted to specify a constant "N"??

You can simply add SR stages to lengthen "N" for my original post.

You can do this with a counter (flip-flops), but cautiously, to avoid glitches/slivers.

...Jim Thompson

Since your "gate" is not synchronous with the "clock" you _will_ have plus/minus 1 on "N", _unless_ you have a programmable counter that you set to "N".

Simple logic solutions can only guarantee no "partial" pulses, not that you only get exactly "N".

...Jim Thompson

Right, I want to control the number of pulses per burst by changing the width of the gate pulse. I see on the Wikipedia entry for flip-flops that using two of them minimizes the probability of the problems encountered when the gate signal happens to come at the same time as a clock signal (glitches/slivers?). I guess this iw what Jason Betts was suggesting, and I will probably try this initially. The shift register trick is a good one for small bursts. thanks, slim

Study John Fields' approach as well. Presettable down counter. Not sure if it's synchronous on both ends, but could be made that way easily.

...Jim Thompson

You keep adding requirements without stating what you're trying to accomplish or the constraints/precision/accuracy of the timing relationships between your clock, gate and whatever other unstated stuff is going on in the system.

It is quite usual for a designer to become fixated on solving some sub-problem when taking a step back would yield a much simpler overall solution.

If you're set on using the gate thingie, you can delay the gate by the time between gate start and the first pulse to be gated. You accumulate delay time at the beginning and add it back on the end. You can do this analogly with a capacitor or digitally with a counter and a faster clock. Depending on the constraints you have or place on your signals, you may not need many bits of counter.

Also depends on whether you have control over how the gate is generated. Can it be ANY width? Or does it have discrete steps that can be relied on when deriving the delayed-gate?

Sometimes, it's easier to bite the bullet and make a state machine out of a GAL20V8. A 20v8 makes a dandy oscillator, counter and control logic. Clock frequency accuracy is not important, cause you're only interested in equal times in and out. I like 20V8's/22V10's 'cause they can be programmed with free tools and no experience...and they come in packages that don't require a microscope to see. And I have a lifetime supply of them. There are surely "better" devices available if you have the tools to use them.

Single chip processor is another option. Once you decide to add one, many other system options become possible. Doesn't take very many "cheap" discrete parts to increase system cost well beyond the cost of a processor.

Much depends on what you're trying to accomplish, how many you're going to build and your preference toward spending more time or more money on development.

On 2008-12-19, Slim Gaillard wrote:

that's part of what I was saying... my other circut was another fixed-length one

I was thinking you might be wanting that!

To do that you need a scale to measure the length of the gate pulse against, a scale that is finer than the pulses you are trying to gate. , one way to do this ould be to use a clock that runs faster than the pulse signal and an up-down counter.

I used a clock that's exactly three times the speed of your pulse clock and phase locked. - easiest way to get that is to generate both from the same source, anyway here's the ltspice schematic.

I only count the early part of the gate pulse (the part that arrives before the first clock pulse is emitted) and then I tack that much extra time onto the end of the trigger pulse.

It's quite possible that this can be done with fewer parts, I stopped when it was working in simulation and reasonably tidy looking

Version 4 SHEET 1 2120 1220 WIRE 1344 48 -336 48 WIRE 1456 48 1408 48 WIRE 1952 48 1456 48 WIRE -336 64 -336 48 WIRE 1296 80 848 80 WIRE 1344 80 1296 80 WIRE -336 160 -336 144 WIRE -256 208 -368 208 WIRE 1456 208 1456 48 WIRE 1520 208 1456 208 WIRE -368 224 -368 208 WIRE -256 224 -256 208 WIRE 416 224 -256 224 WIRE 608 224 480 224 WIRE 688 224 672 224 WIRE -64 240 -208 240 WIRE 608 256 544 256 WIRE 1520 256 1456 256 WIRE 1664 256 1632 256 WIRE -208 288 -208 240 WIRE -192 288 -208 288 WIRE -368 304 -384 304 WIRE -256 320 -256 224 WIRE -192 320 -256 320 WIRE -112 320 -128 320 WIRE -64 320 -64 240 WIRE 544 320 544 256 WIRE 544 320 -64 320 WIRE 656 320 544 320 WIRE 688 368 688 224 WIRE 1456 368 1456 256 WIRE 1456 368 688 368 WIRE 1664 400 1664 256 WIRE 1664 400 -64 400 WIRE -256 448 -256 320 WIRE 16 448 -256 448 WIRE 96 448 80 448 WIRE 96 464 96 448 WIRE 1824 464 880 464 WIRE -64 480 -64 400 WIRE 16 480 -64 480 WIRE 192 480 160 480 WIRE 416 480 352 480 WIRE 640 480 576 480 WIRE 848 480 848 80 WIRE 848 480 640 480 WIRE 1616 496 1552 496 WIRE -112 528 -112 320 WIRE 16 528 -112 528 WIRE 96 528 80 528 WIRE 192 528 176 528 WIRE 416 528 400 528 WIRE 656 528 656 320 WIRE 656 528 592 528 WIRE 1424 544 1424 528 WIRE 1552 544 1552 496 WIRE 1616 544 1616 496 WIRE 16 560 -16 560 WIRE -16 592 -16 560 WIRE 608 592 -16 592 WIRE -304 608 -480 608 WIRE 176 608 176 528 WIRE 176 608 -240 608 WIRE 640 624 640 480 WIRE 640 624 -16 624 WIRE 1424 624 1408 624 WIRE 1664 624 1616 624 WIRE -480 640 -480 608 WIRE -384 640 -432 640 WIRE -304 640 -320 640 WIRE -384 672 -416 672 WIRE -16 672 -16 624 WIRE 16 672 -16 672 WIRE 80 688 80 672 WIRE 96 688 80 688 WIRE -64 704 -64 480 WIRE 16 704 -64 704 WIRE 192 704 160 704 WIRE 416 704 352 704 WIRE 608 704 608 592 WIRE 608 704 576 704 WIRE -416 720 -416 672 WIRE -64 720 -64 704 WIRE -64 720 -416 720 WIRE 1616 720 1616 704 WIRE -112 752 -112 528 WIRE 16 752 -112 752 WIRE 96 752 80 752 WIRE 176 752 176 608 WIRE 192 752 176 752 WIRE 400 752 400 528 WIRE 416 752 400 752 WIRE 1424 752 1424 704 WIRE 1488 752 1488 704 WIRE 1488 752 1424 752 WIRE -432 768 -432 640 WIRE -112 768 -112 752 WIRE -112 768 -432 768 WIRE 992 768 928 768 WIRE 1280 768 1264 768 WIRE 1408 768 1280 768 WIRE 16 784 -16 784 WIRE 928 816 928 768 WIRE 992 816 992 768 WIRE 1408 816 1408 768 WIRE 1408 816 1392 816 WIRE -16 832 -16 784 WIRE 640 832 -16 832 WIRE 1536 832 1520 832 WIRE 1280 848 1280 768 WIRE 1280 848 1264 848 WIRE 1696 848 1696 832 WIRE 1696 848 1680 848 WIRE 608 864 608 704 WIRE 608 864 -16 864 WIRE 1040 896 992 896 WIRE 1408 912 1408 896 WIRE 1536 928 1536 912 WIRE -16 944 -16 864 WIRE 16 944 -16 944 WIRE 192 944 80 944 WIRE 208 944 192 944 WIRE 416 944 352 944 WIRE 432 944 416 944 WIRE 640 944 640 832 WIRE 640 944 576 944 WIRE 1280 944 1280 848 WIRE 1280 944 1264 944 WIRE -64 976 -64 720 WIRE 16 976 -64 976 WIRE 176 992 176 752 WIRE 192 992 176 992 WIRE 400 992 400 752 WIRE 416 992 400 992 WIRE 1280 992 1280 944 WIRE 1408 1008 1408 992 WIRE 1696 1008 1696 992 WIRE 1536 1024 1536 1008 WIRE 880 1056 880 464 WIRE 1184 1056 880 1056 WIRE 1824 1056 1824 464 WIRE 1824 1056 1184 1056 WIRE 176 1088 176 992 WIRE 256 1088 176 1088 WIRE 400 1088 400 992 WIRE 400 1088 320 1088 FLAG -336 160 0 FLAG -384 304 0 FLAG 928 896 0 FLAG 1040 896 pulse_clock FLAG 1552 624 0 FLAG 1664 624 trigger_clock FLAG 1696 1008 0 FLAG 1680 848 sync_out FLAG 1536 1024 0 FLAG 1520 832 output FLAG 1488 624 0 FLAG 1408 624 pulse_clock2 FLAG 352 -192 pulse_clock FLAG 352 -160 pulse_clock2 FLAG 352 -128 trigger_clock FLAG 352 -96 ctr_state FLAG 352 -64 sync_out FLAG 352 -32 output FLAG -480 720 0 FLAG 1408 1008 0 FLAG 1392 816 ctr_state FLAG 1536 752 out FLAG 1952 48 out FLAG 1296 80 sync FLAG 1696 752 sync FLAG 640 480 ctr1 FLAG 1184 768 ctr1 FLAG 1184 848 ctr2 FLAG 608 704 ctr2 FLAG 640 944 ctr3 FLAG 1184 944 ctr3 FLAG -336 48 Pulses FLAG 992 976 Pulses FLAG -256 208 trigger FLAG 1616 720 trigger FLAG -480 608 timer FLAG 1424 528 timer FLAG 1184 1056 0 SYMBOL voltage -336 48 M0 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName V1 SYMATTR Value PULSE(0 1 0 0 0 .00001 .00006) SYMBOL Digital\\\\and 1376 0 R0 SYMATTR InstName A1 SYMBOL voltage -368 208 M0 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName V2 SYMATTR Value PULSE(0 1 0 0us 0us 104u 261.41u) SYMBOL res 976 880 R0 SYMATTR InstName R1 SYMATTR Value 12K SYMBOL res 976 800 R0 SYMATTR InstName R2 SYMATTR Value 1k SYMBOL voltage 928 800 R0 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName V3 SYMATTR Value 1 SYMBOL res 1600 608 R0 SYMATTR InstName R3 SYMATTR Value 12K SYMBOL res 1600 528 R0 SYMATTR InstName R4 SYMATTR Value 1k SYMBOL voltage 1552 528 R0 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName V4 SYMATTR Value .9v SYMBOL res 1712 848 R180 WINDOW 0 36 76 Left 0 WINDOW 3 36 40 Left 0 SYMATTR InstName R9 SYMATTR Value 12K SYMBOL res 1712 944 R180 WINDOW 0 38 67 Left 0 WINDOW 3 36 40 Left 0 SYMATTR InstName R11 SYMATTR Value 1k SYMBOL voltage 1696 912 R0 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName V8 SYMATTR Value .7v SYMBOL res 1552 848 R180 WINDOW 0 36 76 Left 0 WINDOW 3 36 40 Left 0 SYMATTR InstName R12 SYMATTR Value 12K SYMBOL res 1552 928 R180 WINDOW 0 36 76 Left 0 WINDOW 3 36 40 Left 0 SYMATTR InstName R13 SYMATTR Value 1k SYMBOL voltage 1536 912 R0 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName V9 SYMATTR Value .6v SYMBOL res 1440 640 R180 WINDOW 0 36 76 Left 0 WINDOW 3 36 40 Left 0 SYMATTR InstName R14 SYMATTR Value 12K SYMBOL res 1440 720 R180 WINDOW 0 36 76 Left 0 WINDOW 3 36 40 Left 0 SYMATTR InstName R15 SYMATTR Value 1k SYMBOL voltage 1488 720 R180 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName V10 SYMATTR Value .5 SYMBOL Digital\\\\dflop 272 432 R0 SYMATTR InstName A2 SYMBOL Digital\\\\dflop 272 656 R0 SYMATTR InstName A3 SYMBOL Digital\\\\dflop 272 896 R0 SYMATTR InstName A4 SYMBOL Digital\\\\and 48 400 R0 SYMATTR InstName A5 SYMBOL Digital\\\\and 48 480 R0 SYMATTR InstName A6 SYMBOL Digital\\\\and 48 624 R0 SYMATTR InstName A7 SYMBOL Digital\\\\and 48 704 R0 SYMATTR InstName A8 SYMBOL Digital\\\\and 48 896 R0 SYMATTR InstName A9 SYMBOL Digital\\\\or 128 432 R0 SYMATTR InstName A11 SYMBOL Digital\\\\or 128 656 R0 SYMATTR InstName A12 SYMBOL Digital\\\\and -272 560 R0 SYMATTR InstName A15 SYMBOL Digital\\\\or -352 592 R0 SYMATTR InstName A16 SYMBOL Digital\\\\or -160 240 R0 SYMATTR InstName A18 SYMBOL Digital\\\\and 640 176 R0 SYMATTR InstName A13 SYMBOL Digital\\\\inv 416 160 R0 SYMATTR InstName A20 SYMBOL voltage -480 624 M0 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName V5 SYMATTR Value PULSE(0 1 12.5u 0 0 5u 20u) SYMBOL res 1424 912 R180 WINDOW 0 36 76 Left 0 WINDOW 3 36 40 Left 0 SYMATTR InstName R6 SYMATTR Value 1k SYMBOL voltage 1408 896 R0 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName V6 SYMATTR Value .8v SYMBOL res 1280 832 R90 WINDOW 0 0 56 VBottom 0 WINDOW 3 32 56 VTop 0 SYMATTR InstName R5 SYMATTR Value 36K SYMBOL res 1280 752 R90 WINDOW 0 0 56 VBottom 0 WINDOW 3 32 56 VTop 0 SYMATTR InstName R7 SYMATTR Value 36K SYMBOL res 1280 928 R90 WINDOW 0 0 56 VBottom 0 WINDOW 3 32 56 VTop 0 SYMATTR InstName R8 SYMATTR Value 36K SYMBOL Digital\\\\inv 256 1024 R0 SYMATTR InstName A21 SYMBOL Digital\\\\dflop 496 432 R0 SYMATTR InstName A22 SYMBOL Digital\\\\dflop 496 656 R0 SYMATTR InstName A23 SYMBOL Digital\\\\dflop 496 896 R0 SYMATTR InstName A24 SYMBOL Digital\\\\srflop 1568 160 R0 SYMATTR InstName A25 TEXT 520 -40 Left 0 !.tran .02 TEXT 280 -232 Left 0 ;probe thses nodes to get a timing diagram in the scope TEXT 904 504 Left 0 ;This bumf is for\\ngenerating the \\nvoltages for the \\ntiming diagram

--- It's on abse...

news: snipped-for-privacy@4ax.com

BTW, an entire chip (the '08) can be saved by using a diode AND for the output: (View in Courier)

Vcc | [10K] | U2-9

On Fri, 19 Dec 2008 10:57:42 -0500, Slim Gaillard wrote:

--- Following is an LTspice simulation of a way which will allow you to get rid of the external gate and to select any number of pulses by using a programmable counter, where the train will be initiated by a single trigger pulse:

Version 4 SHEET 1 2548 1144 WIRE 960 -976 -512 -976 WIRE 960 -944 960 -976 WIRE -192 -912 -400 -912 WIRE 736 -912 -192 -912 WIRE 32 -896 -176 -896 WIRE 736 -896 32 -896 WIRE 880 -896 800 -896 WIRE 1088 -896 1040 -896 WIRE 256 -880 48 -880 WIRE 736 -880 256 -880 WIRE 480 -864 272 -864 WIRE 736 -864 480 -864 WIRE 704 -848 496 -848 WIRE 736 -848 704 -848 WIRE 880 -848 816 -848 WIRE -512 -816 -512 -976 WIRE -304 -816 -512 -816 WIRE -80 -816 -304 -816 WIRE 144 -816 -80 -816 WIRE 368 -816 144 -816 WIRE 592 -816 368 -816 WIRE -304 -784 -304 -816 WIRE -80 -784 -80 -816 WIRE 144 -784 144 -816 WIRE 368 -784 368 -816 WIRE 592 -784 592 -816 WIRE -304 -688 -304 -704 WIRE -304 -688 -336 -688 WIRE -80 -688 -80 -704 WIRE -80 -688 -112 -688 WIRE 144 -688 144 -704 WIRE 144 -688 112 -688 WIRE 368 -688 368 -704 WIRE 368 -688 336 -688 WIRE 592 -688 592 -704 WIRE 592 -688 560 -688 WIRE -304 -656 -304 -688 WIRE -80 -656 -80 -688 WIRE 144 -656 144 -688 WIRE 368 -656 368 -688 WIRE 592 -656 592 -688 WIRE -400 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WIRE -80 -352 -80 -384 WIRE -80 -352 -304 -352 WIRE 80 -352 -80 -352 WIRE 144 -352 144 -384 WIRE 144 -352 80 -352 WIRE 320 -352 144 -352 WIRE 368 -352 368 -384 WIRE 368 -352 320 -352 WIRE 592 -352 592 -384 WIRE 592 -352 368 -352 WIRE 848 -352 592 -352 WIRE 960 -352 960 -800 WIRE 960 -352 848 -352 WIRE -400 -320 -400 -560 WIRE 816 -320 816 -848 WIRE 816 -320 -400 -320 WIRE -400 -288 -400 -320 WIRE 1088 -288 1088 -896 WIRE 1088 -288 -224 -288 WIRE -416 -192 -416 -224 WIRE -32 -192 -416 -192 WIRE 208 -192 -32 -192 WIRE 736 -192 208 -192 WIRE 976 -192 736 -192 WIRE 1232 -192 976 -192 WIRE 1344 -176 1296 -176 WIRE 464 -160 224 -160 WIRE 848 -160 848 -352 WIRE 1088 -160 848 -160 WIRE 560 -144 528 -144 WIRE 1232 -128 1200 -128 WIRE -160 -112 -304 -112 WIRE 80 -112 80 -352 WIRE 320 -112 320 -352 WIRE 576 -112 528 -112 WIRE 848 -112 848 -160 WIRE 1088 -112 1088 -160 WIRE 464 -96 432 -96 WIRE -64 -64 -96 -64 WIRE 0 -64 -64 -64 WIRE 224 -64 224 -160 WIRE 224 -64 160 -64 WIRE 240 -64 224 -64 WIRE 672 -64 640 -64 WIRE 768 -64 672 -64 WIRE 1008 -64 928 -64 WIRE 1200 -64 1200 -128 WIRE 1200 -64 1168 -64 WIRE -160 -48 -192 -48 WIRE 576 -48 544 -48 WIRE -64 -32 -64 -64 WIRE 672 -32 672 -64 WIRE -192 -16 -192 -48 WIRE -32 -16 -32 -192 WIRE 0 -16 -32 -16 WIRE 208 -16 208 -192 WIRE 240 -16 208 -16 WIRE 432 -16 432 -96 WIRE 432 -16 416 -16 WIRE 544 -16 544 -48 WIRE 736 -16 736 -192 WIRE 768 -16 736 -16 WIRE 976 -16 976 -192 WIRE 1008 -16 976 -16 WIRE 1200 -16 1184 -16 WIRE -192 16 -64 -32 WIRE 544 16 672 -32 WIRE -64 32 -192 -16 WIRE 672 32 544 -16 WIRE -192 48 -192 16 WIRE -160 48 -192 48 WIRE 544 48 544 16 WIRE 576 48 544 48 WIRE -416 64 -416 -192 WIRE -304 64 -304 -112 WIRE -64 64 -64 32 WIRE -64 64 -96 64 WIRE 672 64 672 32 WIRE 672 64 640 64 WIRE -224 112 -224 -288 WIRE -160 112 -224 112 WIRE 576 112 544 112 WIRE -224 144 -224 112 WIRE 544 144 544 112 WIRE 544 144 -224 144 WIRE 672 144 672 64 WIRE 848 144 848 32 WIRE 848 144 672 144 WIRE 1088 144 1088 32 WIRE 1088 144 848 144 WIRE -512 176 -512 -352 WIRE -416 176 -416 144 WIRE -416 176 -512 176 WIRE -304 176 -304 144 WIRE -304 176 -416 176 WIRE 80 176 80 32 WIRE 80 176 -304 176 WIRE 320 176 320 32 WIRE 320 176 80 176 WIRE -512 224 -512 176 FLAG -512 224 0 FLAG 560 -144 HI FLAG -336 -688 HI FLAG -112 -688 HI FLAG 112 -688 HI FLAG 336 -688 HI FLAG 560 -480 HI SYMBOL Digital\\\\dflop -304 -656 R0 SYMATTR InstName A1 SYMATTR SpiceLine vhigh 5v trise 1e-8 tfall 1e-8 SYMBOL Digital\\\\dflop -80 -656 R0 SYMATTR InstName A2 SYMATTR SpiceLine vhigh 5v trise 1e-8 tfall 1e-8 SYMBOL Digital\\\\dflop 144 -656 R0 SYMATTR InstName A3 SYMATTR SpiceLine vhigh 5v trise 1e-8 tfall 1e-8 SYMBOL Digital\\\\dflop 368 -656 R0 SYMATTR InstName A4 SYMATTR SpiceLine vhigh 5v trise 1e-8 tfall 1e-8 SYMBOL Digital\\\\dflop 592 -656 R0 SYMATTR InstName A5 SYMATTR SpiceLine vhigh 5v trise 1e-8 tfall 1e-8 SYMBOL Digital\\\\and -128 -144 R0 SYMATTR InstName A7 SYMATTR SpiceLine vhigh 5v trise 1e-8 tfall 1e-8 SYMBOL Digital\\\\and -128 144 M180 SYMATTR InstName A8 SYMATTR SpiceLine vhigh 5v trise 1e-8 tfall 1e-8 SYMBOL voltage -304 48 R0 WINDOW 3 24 104 Invisible 0 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR Value PULSE(5 0 0 1E-8 1E-8 1E-6 0 1) SYMATTR InstName V2 SYMBOL Digital\\\\dflop 80 -112 R0 SYMATTR InstName A10 SYMATTR SpiceLine vhigh 5v trise 1e-8 tfall 1e-8 SYMBOL Digital\\\\dflop 320 -112 R0 SYMATTR InstName A11 SYMATTR SpiceLine vhigh 5v trise 1e-8 tfall 1e-8 SYMBOL voltage -416 48 R0 WINDOW 3 24 104 Invisible 0 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR Value PULSE(0 5 0 1E-8 1E-8 10E-6 60E-6) SYMATTR InstName V3 SYMBOL Digital\\\\and 496 -192 R0 SYMATTR InstName A12 SYMATTR SpiceLine vhigh 5v trise 1e-8 tfall 1e-8 SYMBOL Digital\\\\and 1264 -224 R0 SYMATTR InstName A15 SYMATTR SpiceLine vhigh 5v trise 1e-8 tfall 1e-8 SYMBOL Digital\\\\or 768 -944 R0 SYMATTR InstName A6 SYMATTR Value2 vhigh 5v trise 1e-8 tfall 1e-8 SYMBOL res -96 -800 R0 SYMATTR InstName R2 SYMATTR Value 10K SYMBOL res -320 -800 R0 SYMATTR InstName R1 SYMATTR Value 10K SYMBOL res 128 -800 R0 SYMATTR InstName R3 SYMATTR Value 10K SYMBOL res 352 -800 R0 SYMATTR InstName R4 SYMATTR Value 10K SYMBOL res 576 -800 R0 SYMATTR InstName R5 SYMATTR Value 10K SYMBOL res -320 -480 R0 SYMATTR InstName R6 SYMATTR Value 10K SYMBOL res -96 -480 R0 SYMATTR InstName R7 SYMATTR Value 10K SYMBOL res 128 -480 R0 SYMATTR InstName R8 SYMATTR Value 10K SYMBOL res 352 -480 R0 SYMATTR InstName R9 SYMATTR Value 10K SYMBOL res 576 -480 R0 SYMATTR InstName R10 SYMATTR Value 10K SYMBOL Digital\\\\dflop 960 -944 R0 SYMATTR InstName A16 SYMATTR SpiceLine vhigh 5v trise 1e-8 tfall 1e-8 SYMBOL Digital\\\\and -480 -256 R270 SYMATTR InstName A9 SYMATTR SpiceLine vhigh 5v trise 1e-8 tfall 1e-8 SYMBOL Digital\\\\and 608 -144 R0 SYMATTR InstName A13 SYMATTR SpiceLine vhigh 5v trise 1e-8 tfall 1e-8 SYMBOL Digital\\\\and 608 144 M180 SYMATTR InstName A14 SYMATTR SpiceLine vhigh 5v trise 1e-8 tfall 1e-8 SYMBOL Digital\\\\dflop 848 -112 R0 SYMATTR InstName A18 SYMATTR SpiceLine vhigh 5v trise 1e-8 tfall 1e-8 SYMBOL Digital\\\\dflop 1088 -112 R0 SYMATTR InstName A19 SYMATTR SpiceLine vhigh 5v trise 1e-8 tfall 1e-8 TEXT -456 208 Left 0 !.tran 0 2400E-6 0 uic TEXT 1360 -176 Left 0 ;OUT

JF