fooling the compiler

John Larkin · 2010-06-25T05:09:33+00:00

We have a Spartan6/45 that's talking to 16 separate SPI A/Dconverters. The data we get back is different, but the clock and chipselect timings are the same. To get the timing right, avoiding routingdelays, we need our outgoing stuff to be reclocked by i/o cellflipflops.So what happens is that we have one state machine running all 16 SPIinterfaces. We tell the software that we want the adc chip selectflops in i/o cells. The compiler decides that all are seeing the sameinput signal, so reduces them to one flipflop. Then it concludes thatthat flipflop can't be in an i/o block, and builds it that way. Theresulting routing delays are deadly.We couldn't find a way to force these 16 flops into IOBs. Really.The fix is to fool the compiler into thinking the flipflop states arenot the same. Turns out the the synchronous clear inputs to the flopsare unused in our design. My suggestion was to ground an input pin,run that into the serial input of a 16-bit shift register, and routethe sr taps to the clears of the 16 output flops. The compiler can'tknow that these levels are in fact always low, so has to gen 16different flops. *Then* it allows the flops to be forced into IOBs.Rob has a better idea, just make a 16-bit SR that generates athermometer code on powerup, namely walk a 1 into it, and have the sroutput bits un-clear the i/o flops sequentially. The compiler isn'tsmart enough catch onto that, and we don't need to ground a pin.It works.Isn't that all perfectly stupid?The Altera folks are coming to make their pitch tomorrow. This storymay amuse them.John

Jun 25, 2010 21 Replies

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Nico Coesel 16 years ago

Another way to force flipflops in an IOB is to specify a short delay for the output flip-flop to pad path.

Failure does not prove something is impossible, failure simply indicates you are not using the right tools... nico@nctdevpuntnl (punt=.) --------------------------------------------------------------

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krw 16 years ago

The problem I see with that is that it can't be verified (what can, I suppose) until after PAR is run. By using synthesis attributes the results can be seen in the technology view (or whatever they call it today).

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fooling the compiler

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