I don't know, Lasse. Maybe leakage affects their operation, but that's just a guess. If you use parts way outside their specs and in small quantities, manufacturers tend not to be interested in such questions.
I'm just looking at MiM caps for a 100MHz fixed frequency oscillator (with initial electronic trim, 4-bits, to account for basic process tolerance), TC=33u, so 0.5% increase from 27° to 180°.
So my guess, if you're having problems, is that it is the CMOS itself... CMOS slo-o-o-ows down at high temperatures.
I did some DLL stuff for Silicon Graphics, Chippewa Falls, WI, wa-a-a-ay back ~1996. Synchronizing 4 separate chips to a master clock. It was rated to 200°C.
Is your FPGA designed to be a DLL? ...Jim Thompson
--
| James E.Thompson, CTO | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona 85048 Skype: Contacts Only | |
| Voice:(480)460-2350 Fax: Available upon request | Brass Rat |
| E-mail Icon at http://www.analog-innovations.com | 1962 |
I love to cook with wine. Sometimes I even put it in the food.
Aha! I had forgotten the tapped buffer delay-line approach. That fails at very hot... can't meet minimum delay... if you're pushing it. ...Jim Thompson
--
| James E.Thompson, CTO | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona 85048 Skype: Contacts Only | |
| Voice:(480)460-2350 Fax: Available upon request | Brass Rat |
| E-mail Icon at http://www.analog-innovations.com | 1962 |
I love to cook with wine. Sometimes I even put it in the food.
You mean you've tried on-chip PLLs and DLLs. Perhaps a roll-your-own PLL feeding the FPGA would work.
--
My liberal friends think I'm a conservative kook.
My conservative friends think I'm a liberal kook.
Why am I not happy that they have found common ground?
Tim Wescott, Communications, Control, Circuits & Software
http://www.wescottdesign.com
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