FIR chips

That wouldn't take a lot of power in a small FPGA. What's the transfer function look like? What's your power budget?

An FIR filter doesn't necessarily need to be a classic shift register/multiplier/summer thing, with all those multiplies and adds. Boxcars and such are, technically, FIR, but don't work as hard. And there are folding tricks and stuff to keep the power down.

An FPGA is about the only game in town, excepting maybe a DSP processor.

--

John Larkin, President
Highland Technology, Inc

jlarkin at highlandtechnology dot com
http://www.highlandtechnology.com

Precision electronic instrumentation
Picosecond-resolution Digital Delay and Pulse generators
Custom laser controllers
Photonics and fiberoptic TTL data links
VME thermocouple, LVDT, synchro   acquisition and simulation

It's a correlation filter, so I need the multiplies. I *must* avoid BGA devices, so that limits the FPGA size - I may have to split it between devices if that's the way I have to go.

Cheers

--
Syd

You should be able to find an FPGA in a leaded package that'll do that. It really is a small task, these days -- I'd start by looking at whatever Xilinx's latest Spartan part is; I think you'll be hard pressed to find one that _doesn't_ have over 2k-bits of block RAM; whether you'll find one with enough and multipliers to do the job is a question, because with

128 taps you'll need to run it pretty fast.

--
Tim Wescott
Control system and signal processing consulting
www.wescottdesign.com

You should be able to do this in a leaded FPGA. You don't need a lot of pins: 16 in, 16 out, some sort of port to load coefficients (unless you want to compile them in.) Splitting this up will probably add more interconnects and delays than it's worth.

I think some of the FPGA design suites will generate an FIR for you; I'll ask my FPGA guy about that.

At 30 MHz, you should be able to share multipliers 4x or maybe 8x, so you only need 32 or maybe even 16 MACs. That's not a big chip.

--

John Larkin, President       Highland Technology Inc
www.highlandtechnology.com   jlarkin at highlandtechnology dot com   

Precision electronic instrumentation
Picosecond-resolution Digital Delay and Pulse generators
Custom timing and laser controllers
Photonics and fiberoptic TTL data links
VME  analog, thermocouple, LVDT, synchro, tachometer
Multichannel arbitrary waveform generators

BGA

Or Altera's Cyclone series.

Though, if implementing FPGA, be aware that FPGA's real power comes from 'parallel' processing, and to really take advantage of their architecture requires a bit of rethinking. The good side, 30MHz is slow and speed is power, plus since you don't need any PLL's running you should save a bit of power there.

"Syd Rumpo" a écrit dans le message de groupe de discussion : jk4ojq$lhs$ snipped-for-privacy@dont-email.me...

Hi Sid,

You may have a look at Intersil, HSP43220 and similar. Not sure about the low power and may be a little expensive as compared to a small FPGA but that will give you an alternative...

Friendly yours,

Robert Lacoste

I think the least expensive solution, probably in power and certainly in chips, is going to involve jacking the clock up -- probably to somewhere between 120 and 300MHz -- as well as doing parallel processing.

Trying for 128 parallel 16-bit paths is going to be asking for an enormous chip.

--
My liberal friends think I'm a conservative kook.
My conservative friends think I'm a liberal kook.
Why am I not happy that they have found common ground?

Tim Wescott, Communications, Control, Circuits & Software
http://www.wescottdesign.com

BGA

afaikt from a quick look the biggest xilinx you can get in a non-bga is something like XC3S500E with 20 multipliers and 360kbit block ram so a little over 200MHz and it shouldn't impossible

-Lasse

Thanks, Robert and everybody for your input. The Intersil (formerly Harris - I'd forgotten) chip looks good although it may be too large physically. I'd omitted to mention that I can't have very high clock speeds, certainly not hundreds of MHz, so still a bit undecided.

Cheers

--
Syd

why no high speed clocks? EMC issue?

high speed clocks sometimes are 'internal'

it's a decimating filter, first filter is integrate and dump, last part is a fir filter to correct the response and it only has a single multiplier so it will not do anything like a fir filter with 128 taps and 30MHz input and output rate

most FPGAs will have some form of clock muliplier available so the fast clk will only be internal

-Lasse

Ah yes, I see - I just looked at the headline figures on the front page. Looks like FPGAs then. I can't use clock multipliers as they're unreliable at the out-of-spec temperatures I need as are very high speed external clocks.

Cheers

--
Syd

What are 'out of spec temperatures'? You can always choose to do your own qualification.

--
Failure does not prove something is impossible, failure simply
indicates you are not using the right tools...
nico@nctdevpuntnl (punt=.)
--------------------------------------------------------------

Yes, that's how I know clock multipliers aren't reliable.

Cheers

--
Syd

how much out of spec? all kinds of clock multipliers? Xilinx use a delay locked loop, not a pll

-Lasse

IME at 180'C ambient neither PLL nor DLL are reliable :-(

Cheers

--
Syd

You're talking generalities backed by no facts. ...Jim Thompson

--
| James E.Thompson, CTO                            |    mens     |
| Analog Innovations, Inc.                         |     et      |
| Analog/Mixed-Signal ASIC's and Discrete Systems  |    manus    |
| Phoenix, Arizona  85048    Skype: Contacts Only  |             |
| Voice:(480)460-2350  Fax: Available upon request |  Brass Rat  |
| E-mail Icon at http://www.analog-innovations.com |    1962     |
             
I love to cook with wine.     Sometimes I even put it in the food.

Well, I have tried various FPGAs at elevated temperatures, as have others, and any PLL/DLL seems to be often the first thing to fail and none that I've tested or know about will operate at 180'C. I'm afraid test details are not generally shared and that's not something I can change.

I don't know why this should be, possibly on-chip capacitors, but I'd be grateful for any insight a chip designer could bring.

Cheers

--
Syd

if you can't do BGA you are limited to small(er) FPGAs if you can't do high frequencies, don't any other option than several FPGAs

the right clock doubler should work as long as the part works so you need 64 mulipliers at 60MHz, you can get

16 or maybe 20 mults in a xilinx FPGA if you want non-bga so 4 * 100tqfp and a config flash

-Lasse