Most DDS theory uses sine waves. There could well be a better waveform, like a trapezoid, but that's going to need a lot of simulation to evaluate.
Just dividing some low jitter oscillator is as
DDS has arbitrary frequency resolution and, potentially, very low jitter. Divisors have low jitter but quantify the frequency selections hard. Our users can already select the internal XO and a divisor. In fact, they can program a burst of N pulses every M pulses no matter what the clock source.
That's illogical. Firstly, the output of the sine table is parts-per-thousand steps, not 'coarse' in the voltage sense, and you can dither and interpose as many time steps of alternating values as you care to. Coarse in time is a choice, not a requireent.
Second, a filter does not 'interpolate' a time sequence, it only has access to the PAST of the signal.
Most vitally, in the Fourier-trasform sense, a frequency is DEFINITIVE of a sine, and no other signal, after filtering, has an unchanged 'frequency' character. If there's a filter involved, a sine is the One True Input form that gives you an output frequency to rely on. You aren't making a mess (or knife-fighting with "messer" items) when you consult a sine table, but are gathering wisdom from an oracle.
How is that different? Are you trying to say interpolation looks at future samples? Delay that interpolation output and you get the exact same thing as the filter output that only looks at past samples.
The problem people are concerned about with the sine wave is that the slope is so shallow, that a very small amount of noise adds a large amount of jitter.
Why can't people understand that the DDS can use a sine wave at the highest frequency, over a 2:1 range of frequency to generate the fundamental with very low jitter? This signal can be run through a programmable divider to divide the DDS output by octaves to obtain any lower frequency you wish, with the same jitter, other than jitter introduced by the logic implementation. This jitter can be removed by running the output through a FF of some technology that restores the jitter of the DDS output.
None of this nonsense of trying to implement trapezoids is needed.
If one wants 'interpolation', an FIR filter, applied in advance of the D-to-A step, can easily perform it; a real-components analog filter, though, cannot be described as an interpolation unless one has some kind of way of blinding the filter to the past AND the future of a time interval (maybe with delay lines?). The arrow-of-time is absent in true interpolation.
<snip>
The 2:1 range sine generator followed by divider would work. So would a trapeziod generator. The questions are which would be cheaper which is an interesting question and which would perform better, which isn't all that interesting because they'd probably perform identically if competently executed.
and you can dither and interpose as many time
Any real lowpass filter has time delay. So relative to its output, it is blending past and future inputs.
As far as I can see you are going to do sine wave. In that case I would do as much brute force as is practical - the is, as long a sine lookup table as possible - and then interpolate. Those dsp sections they put in fpga-s must be kept busy? 10 ns is not a lot of time to do it but it must be doable. And second or even third order interpolation is not that hard - and can probably give you virtually error free values even for the 1mHz case. Easier said than done I suppose but that's the advantage of giving an opinion and not having to deliver the goods.... :D.
It has been suggested that, at low frequencies, we interpolate between sine table entries so we can keep approximating the sine wave at the
100 MHz clock rate, instead of making a step now and then as the selected MS bits of the phase accumulator tick over. That does still make a slow sine wave at the lowpass filter output.Straight-line interpolation is probably good enough for short segments of a sine. The interpolation slopes could be another lookup table.
The idea of making a perfect DDS clock is a deliciously complex problem. Just thinking about it is educational.
That could work, but looks somewhat suboptimal. Generally, let us assume that we try to generate some periodic f(t) and pass result to comparator. Due to discrete nature of syntesis we will have some error, call it r(t). So comparator instead at zeros of f(t) will switch at zeros of f(t) + r(t). Assuming that error is resonably small we can estimate shift of zero using deriavative of f: delta t_0 \approx -r(t_0)/f'(t_0). So, to have best accuracy we want:
- have f' at zeros of f as big as possible
- have r as small as possible
Let us first look at r, there are two components to error. One is discretization error of voltage level due to finite resulution from DAC. Second, due to discrete time we get mirror freqencies. More precisly, when
f(t) = \sum_n c_n \exp(iw_1nt)
(where i is imaginary unit), and w_1 pulsation of f, discrete time version g(t) has form
g(t) = \sum_n \sum_m c_n \exp(i(w_1n + w_2m)t)
where w_2 is pulsation of DAC clock. We apply low pass filter to eliminate unwanted high frequencies. It seems that frequent choice is filter with bandpass up to w_2/3 and delivering string attenuation at 2w_2/3. Now, if |w_1n + w_2m| < w_2/3 mirror freqency will be in bandpass. For m not equal to 0 it means that c_n should be very small, preferably 0 (othewise we will get error which can not be removed by filtering). In other words, to avoid error immune to filtering we want c_n to be 0 when |w_1n| > w_2/3. So f(t) should be trigonometric polynomial with frequencies satifying condition above.
Now, we want f which has fast transition trough 0. Obvious choice is trigonometric approximation to square wave. This has horrible ringing. Theoretically, if phase shifts vary within 20-30 degrees over bandpass ringing should be no problem. If ringing turns out to be problematic one can reduce it using trigonmetric approximation to trapezoidal waveform, getting slower transition.
Educational it certainly is, I'd say it will take more brute force than complexity but it is clearly a lot harder than it seems at first glance. I'd make sure I have the horsepowers in case linear interpolation is not good enough and I'd have to go second or third order... I have not experience with these fpga dsp sections but I have seen some have dozens of them, the interpolation needed can be parallelized as much as it takes. Dealing with the heath may also be needed :).
Ok, so you are picking a nit. I'm not aware of any definition of "interpolate" that requires it be limited to inputs of specific samples. It simply means values are inserted. I've seen digital interpolation by inserting samples with values of zero and having no correspondence to the samples on the input stream.
If you want to *average* in analog, I can do that with sample and holds and an opamp to combine the two values. Not so har really.
I did a quick misuse of my filter editor to draw a sine wave and see what interpolation looks like. 64 points, interpolated into
16384 points. You'll need a lot more than that but this might give an idea. The linear interpolation looks edgy, but the difference between second ad third order interpolation is practically invisible at this scale.<snip>
No real low pass filter is ever going to blend in future inputs. The output is a weighed sum of past inputs, but future inputs are inaccessible.
The most recent past input won't have much effect on the output - that's the time delay through the filter - bu there's a whole load of theory that spells that out in detail. Read Williams and Taylor.
Actually, it is fundamental to the digital domain. You have to start off with one low jitter clock, and every digital output is clocked out by that single clock.
The whole point of the low pass filter in a DDS set-up is to cope with with the fact that you've only got one set of clock edges to play with.
All true. But without the low pass filter, the staircase artefacts add a lot of higher frequencies into your One True sine wave. That's what John Larkin is rather ineptly wresting with.
What about the zero-crossing region? That's the critical area. Cubic may be best there.
Joe Gwinn
For a sine wave the zero crossing is the point where the function is perfectly linear.
I think this train of thought is out of control. The easy and optimal solution is the bog standard DDS with a long phase accumulator, a well constructed tables for the sum of angles sine equation, and a quality DAC followed by a good low pass filter and comparitor. This only needs to operate over a 2:1 frequency range since all lower frequencies can be generated by a programmable divider from the DDS output. No fuss, no muss and it can be done by next week. It's not like this is a new problem.
The idea of generating a trapezoid waveform over a wide frequency range means reloading the lookup table every time you change the frequency.
<snip>
That's exactly what it avoids.The sloped bits of the trapezoid were to have exactly the same slope no matter what frequency is being generated. Same slope, same low pass filter. Massive simplification.
Really fast 14--bit DACs aren't cheap, but once John Larkin specified his maximum frequency to be 15MHz, and his master clock frequency as 100MHz, slower cheaper DACs would be worth looking for, if there was any prospect that he'd pay any attention.
I'll screenshot it tomorrow, now I am briefly awake only... :) [some noise woke me up, stopped when I turned on the light; was very faint, I lay listening for may be 2-3 minutes. May be some insect or something...).] I looked at the zero crossing region, it is the steepest and closest to linear. Perhaps the top was the least linear, did not look too much though. But if just the zero-crossing were the problematic area no sine would be necessary anyway (which is what I thought once I knew it was about just triggering something but John wants a perfect sine).
But, if you decide on a thousand-point table for the DAC to perform, all it takes is a tiny bit of logic in a tight-time loop to weighted-sum two DAC outputs, one for the last sample another for the next sample, in analog summing-junction style, thus actually doing an interpolation as mentioned. Even though the points as DAC-generated number only a thousand, you don't need to have a thousand-step staircase, it could also be a finer staircase hitting those thousand marks, but microstepping between.
My preference would be to do that all analog, phase-locking to make the inner clock for the lowest output frequencies. Needn't be any microstepping, if current-steering is run by a trianglewave VCO.
Sounds good on the downstream side, but how do you generate the samples to feed the DAC? If you want to have variable frequency, you need to adjust the lookup table for every frequency you choose. How else are you generating the DAC samples?
You can't just load the table with one set of values and expect it to generate the same slope for every frequency. If you use the same LUT for a slow and fast output frequency, the fast output frequency would have a large enough step size through the LUT to literally skip over the ramp. At sufficiently low sample rates, the slow again turns into a slow ramp.
Is this about no LUT at all? Just using the LSBs of the phase ramp? But that still gives you varying ramp slopes.
ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.