Direct digital synthesis of square waves (2023 Update)

What puzzles me is how John Larkin finds customers dumb enough to be impressed by this kind of meaningless twaddle.

A DDS doesn't generate ticks. It generates a staircase approximations to sine waves. John Larkin's mode of thinking about what's going on is definitely a mess.

The treads on the staircase are very close together - with 14-bit DAC there are 16,384 of them - and each one can sit there for a while.

So what?

AKA "CORDIC"

If all you want to do is to generate a trigger at any frequency from

10^-3 Hz to 15*10^6 Hz in 10^-3 Hz steps, that is easily done in a phase-only DDS topology (no trig conversion needed), which can be implemented directly in a FPGA.

This is also known as a Numerically Controlled Oscillator:

.

Our output would be point /M in Figure 1 in the above Wiki article. (Never mind that M is actually a bit width in that figure.)

How big must the accumulator be? 15*10^6/10^-3 = 15*10^9 possible frequencies. Log2[ 15*10^9 ] = 33.8 bits. There was also talk of needing 50^10^9 steps, which would be 35.5 bits, minimum. In either case, a 48-bit accumulator will work with room to spare.

If not, simply make the accumulator larger - 64 bits is also common. One can also choose the clock rate for convenience given the chosen accumulator length.

The trigger signal is when the accumulator rolls over. If the Frequency Control Word is small, this will take some time. If large, much faster.

Joe Gwinn

onsdag den 17. august 2022 kl. 19.02.50 UTC+2 skrev Joe Gwinn:

did you miss the whole discussion?

doing that with say a 100MHz clock give you 10ns jitter, which might be ok low frequency, but terrible at 15MHz

The lowpass filter, between the DAC and the comparator, smooths the samples and reduces the jitter to picoseconds.

The real jitter problem is at low frequencies where the filter doesn't help much.

I was doodling a lowpass filter that is sort of adaptive, to help the low-end jitter. Mr Shannon was a nice guy, but we aren't trying to reproduce a signal, we just want to make a clock.

By 'doodling', I trust you mean that the tracking filter isn't looking like a good solution.

Oh, no, you already HAVE a clock, what you want is a derived infinitely-adjustable variable clock based on that digital clock source.

An easy way, is to use integer-ratio phase locking to the master clock to generate a digitally adjustable clock#2, for coarse adjustments, and use a sinewave variable oscillator (yeah, LC and varactor or moving parts) which can be metered by the master clock and fine-adjusted, then with a diode mixer combine the two.

One discrete-time oscillator and one infinitely-adjustable oscillator, and a mixer. Follow up with an IF-style filter to make sinewaves, then amplifier to make 'em square. 'Tracking filter' functionality is exactly the LC oscillator feature that a totally digital system is missing, and gives you the ability to fill in the gaps in an N/M synthesis.

Mr. Shannon assures us that there will be jitter, as does quantum mechanics, and thermodynamics. Making it small enough is your only option; frequency, for instance, is UNDEFINED mathematically, except for long time scales (it isn't just warmup time that makes a precise frequency measurement of long duration).

onsdag den 17. august 2022 kl. 21.07.20 UTC+2 skrev snipped-for-privacy@highlandsniptechnology.com:

sure but not if you make the square wave directly from the MSB of the accumulator with no DAC

you could also question how much 10ns of jitter matters on a 1Hz signal, it's 10ppb how accurate is the oscillator over a second?

Thinking is not a bad thing to do now and then. And I said adaptive, not tracking.

I'd have to simulate it to see if it's worth doing, and what the side effects might be.

The Sampling Theorem describes a sampled system that perfectly reproduces its input. No time delay even.

Someone noted that most of the great Nobel scientists at Bell Labs had one thing in common: they ate lunch with Harry Nyquist.

In a sense, yes. Thus the call for a re-baseline.

Well, I didn't mention it, but there are some classic dodges:

Pre-packaged full DDS units are made to fit presumed markets, and may not fit the uncommon requirement. But if one implements the NCO plus sinus conversion in a FPGA and uses the output to drive a ADC chip, it's easy to get many more bits of analog width.

First is to use a wider DAC to convert phase to sinus voltage; this will smooth the jaggies at 15 MHz (which is pretty slow by current DAC standards.

Second is to have two paths in parallel, we'll call them fast and slow, with their analog outputs combined by means of a crossover network of some kind.

Third is to multiply the 200 MHz up to say 800 MHz, limited only by the FPGA.

Or some combination of all above.

Joe Gwinn

The phase accumulator MSB is pretty good at low frequencies and hideous at high frequencies. Possibly we can make a reasonably clean transition from sinewave DDS to MSB only at some frequency.

1 PPM RMS jitter would be OK. We're redesigning a product, and the old one uses an ADI spi-interface DDS chip that has horrible jitter at low frequencies, something like 100 PPM.

A customer can program it high and kick in a divisor, which reduces jitter radically, but the transition to a new frequency is messy and some people whine about blown-up lasers or something silly like that.

Our XO can be locked to a better oscillator, and we have an internal OCXO option. Only a few per cent of our sales have the OCXO.

It's pretty good, but I want to make it better next rev. Prettier too.

onsdag den 17. august 2022 kl. 23.49.21 UTC+2 skrev snipped-for-privacy@highlandsniptechnology.com:

just add a frequency dependent gain so the the slew rate stays roughly the same, then there is no transition

I still don't understand why someone would need sine wave for triggering rather than just some TTL or whatever pulse generator, you must have made dozens of these. Just dividing some low jitter oscillator is as trivial as it can get. But if it has to be sine wave well, things do get complicated. I anticipate once you have made that superb sine wave generator they will find out that noise or whatever is a source of some jitter to which the generator's will be negligible.... I don't know the application of course, this is how it looks to me at this point.

try generating arbitrary frequencies that isn't necessarily a multiple of 10ns with a 100MHz clk with just a divider...

Obviously you can't do that, I am just wondering about the application that needs 10 seconds period with picoseconds of jitter. Or with a ns of jitter, for that. But other people asked about making sort of the same thing, clearly there is some demand.

the discussion is about making a dothat that does everything from 10 sec to ~60ns periods with low jitter in all cases and no weird transitions

Irrelevant; the OTHER Shannon work is information content limited by bandwidth and signal/noise, and... the 'ideal' zero-jitter constant frequency with a broad frequency range just has too much information content; whatever number of bits you use to describe the output frequency, it's not enough bits.

My proposed 'IF filter' solution only covers a limited bandwidth, by intent; you'd use regular old synchronous counters to divide down the (high) frequency to your target; jitter at low frequency is assuredly not high.

The problem is the jitter is a full clock cycle. That's the point of generating a sine wave, then filtering it. The zero crossing is no longer aligned to the master clock and you have a new clock related by the ratio of two large integers, so lots of resolution and low jitter.

Ok, generate a 1.23456789 MHz clock from a 100 MHz reference using simple digital dividers.

The sine wave is how the jitter is reduced to as close to zero as you can afford with the filtering.

divide by 81 ;)