Digital wireless systems

I still don't know the OP's requirement for data rate, it's still ambiguous; however, I meant to use the FPGA as the 2nd stage down- conversion and the demodulator both. The whole receiver (all COTS):

1) 5.8 GHz BPF 2) Mini-circuits mixer 3) Fixed L.O. (with amp) 4) IF amp (assume a 1st I.F of about 1.2 GHz) 5) IF filter (e.g. EPCOS) - don't use SAW unless triple-transit ok. 6) ~500 MSPS converter (with at least 1200 MHz BW) 7) FPGA: Cyclone 3, Spartan, Virtex5, etc ...

The above is for 72Mbits/s. If it's only 1.5 Mbps, then it can be a lot simpler. Step 4,5,6 could be adapted for direct conversion, which would be cheaper, but lower performance.

Frank

Hi, Its continous transmission no breaks, just unidirectional communications. So, if I lowered the clock to lets say 500kHz then nordic and Micrel chips would be ok to work with.

John

Not enough details (especially the data rate) on your first link. Can't access your second link. If you email them to me, I will take a look.

contact me at www dot linnix dot com

Hello,

What inofmation do you require? Please let me know.

Regards, John

For the first link. I don't think you need the 8051, if you already have an FPGA. I can't read the second link, so I can't tell if it's the right chip or not. If you have the datasheet somewhere, just email me.

I believe your original problem statement was 48bits per word, transmitting continuously at 1.5 Mb/s. Neither chip will help you. Your data rate is beyond what can handle. For the Micrel transmitter you would have to cut the data rate down to 100kb/s. It may be possible to use the WiMAX Chip but you will now eat batteries.

You should look for 1.5 to 2Mb/s chips for ISM bands, and narrow beam antennas.

After re-reading some of your posts, it seems clear that your data rate is 72 Mbps. It would help to know if this is a one-off (feasibility) or a design project ... Since you already have a Spartan on the transmit side, you can use it as a modulator (e.g QAM), followed by an up-converter, and use another FPGA after down- conversion on the receive side. I think questions about what "chips" to use for the RF (or optical) section might be more productive after we know more about the cost / size and power constraints.

Frank Raffaeli

John wrote on 5/12/2008 > Hi, >

Clear as mud.

Hi,

1.5MHz is the serial clock rate. So, the time period of this clock will be approx. 66 ns. Now, at each rising edge of the clock, FPGA puts a bit out and keep it at its output for one clock cycle. So, FPGA uses 48 clock cycles to output 48 bits. So, according to my guess the data rate to transmit one 48 bit frame is (66ns x 48 = 32usec)....The time interval between two consective 48 bit frames can be anything... I can transmit one after another or can have some delay between them.

Now , I need a wireless system that can transmit and recieve this data, clock and a synch. I heard that I can use FSK technique to do this by programming FPGA as modulator and demodulator. or I can interface FPGA with the some RF chips that can handle this data rate. So, I am looking into chips. I can lower the data clock to 600kHz.

The chips links that I found are as follows

John

This is your internal data clock. You have to buffer the data and shift out at a lower rate.

You have to lower it to 128khz for the Micrel chip

Hi,

By 128khz, you meant the Data clock frequency. Am I right?

John

First you say 1.5M clock, 48 bits at 1.5 MHz, then 66nS, It's difficult to know what you mean.... If you want to call me, I'll help you sort it out. I can help you if you want (I have the day off), but I think it will go 100x faster by phone.

Sorry if you are unable or unwilling to read the whole thread. It might make better sense to you then. Not that it is all that clear in the first place. OP has been given several offers of professional advice (probably paid for). I have no idea if OP has pursued them.

You got it. OP does not seem to understand what the actual requirements are.

Looking at this differently...

Is there perhaps a *smarter* system level way for you to achieve the same end result? i.e. do you have to actually output that amount of data continuously to the DAC via the wireless interface? Does the DAC output anything repetitive that you can automate on the receiver side? e.g. if it's say for example a sine wave bust, can you send a short "generate sine wave burst" "command" instead of the huge amount of actual DAC data itself?

Dave.