Using the SSC on the ARM processor

"dave" skrev i meddelandet news:42ad27ea$ snipped-for-privacy@quokka.wn.com.au...

If you are referring to the AT91RM9200 then the SSC is not "broken". I know of people that wrote a Linux driver and got it to play sound. This driver has not been completed unfortunately. The SSC supports I2S easily. AC97 is more complex to use and you probably should talk to a local contact about that.

--
Best Regards,
Ulf Samuelsson
This is intended to be my personal opinion which may,
or may bot be shared by my employer Atmel Nordic AB

ARM9 does not have SSC, ARMxx is just a processor core. What processor are you using?

Vadim

Hello,

The processor is the AT91RM9200.

Connections: TF --> FSYNC (frame synch 8kHz)

TK --> PCLK (clock 256kHz)

TD --> DRX

RD --> DTX

TFMR -- AT91_SSC_TFMR_FSOS_POSITIVE | // output frame synch is rising

((state->synchLen numData numBits & AT91_SSC_TFMR_DATLEN) | // transfer bit count

0);

TCMR --(((state->period delay synchLen numData numBits & AT91_SSC_RFMR_DATLEN) | // receive bit count

0);

RCMR --(((state->period delay = NUM_BLOCKS)

sscTxBufOut = 0;

HAL_WRITE_UINT32(sscState.sscBase+AT91_SSC_TPR, phys_addr);

HAL_WRITE_UINT32(sscState.sscBase+AT91_SSC_TCR, TX_BLOCK_SIZE);

phys_addr = sscState.physTxBuffer + (sscTxBufOut * RX_BLOCK_SIZE);

//phys_addr = getPhysTxOffset(sscState.physTxBuffer, sscTxBufOut);

if (++sscTxBufOut >= NUM_BLOCKS)

sscTxBufOut = 0;

HAL_WRITE_UINT32(sscState.sscBase+AT91_SSC_TNPR, phys_addr);

HAL_WRITE_UINT32(sscState.sscBase+AT91_SSC_TNCR, TX_BLOCK_SIZE);

// start the transfer

HAL_WRITE_UINT32(sscState.sscBase+AT91_SSC_PTCR, AT91_SSC_PTCR_TXTEN);

// enable tx interrupts

sscIrqMask |= (AT91_SSC_IER_TXBUFE | AT91_SSC_IER_ENDTX);

HAL_WRITE_UINT32(sscState.sscBase+AT91_SSC_IER, sscIrqMask);

#endif

AT91F_SSC_EnableTx(&sscState);

}

//

void sccStartReceive(void)

{

unsigned int phys_addr;

// ready the DTMF decoder, as we are about to start the PCM receiver

initDTMFDecoder();

sscReceiving = 1;

#ifndef NO_PDC

// start the receiver

phys_addr = sscState.physRxBuffer + (sscRxBufIn * RX_BLOCK_SIZE);

//phys_addr = getPhysRxOffset(sscState.physRxBuffer, sscRxBufIn);

if (++sscRxBufIn >= NUM_BLOCKS)

sscRxBufIn = 0;

HAL_WRITE_UINT32(sscState.sscBase+AT91_SSC_RPR, phys_addr);

HAL_WRITE_UINT32(sscState.sscBase+AT91_SSC_RCR, RX_BLOCK_SIZE);

phys_addr = sscState.physRxBuffer + (sscRxBufIn * RX_BLOCK_SIZE);

//phys_addr = getPhysRxOffset(sscState.physRxBuffer, sscRxBufIn);

if (++sscRxBufIn >= NUM_BLOCKS)

sscRxBufIn = 0;

HAL_WRITE_UINT32(sscState.sscBase+AT91_SSC_RNPR, phys_addr);

HAL_WRITE_UINT32(sscState.sscBase+AT91_SSC_RNCR, RX_BLOCK_SIZE);

// Enable the interrupts on the SSC

HAL_WRITE_UINT32(sscState.sscBase+AT91_SSC_PTCR, AT91_SSC_PTCR_RXTEN);

// notify errors, notify all buffers full, notify one buffer full, chain next

sscIrqMask |= (AT91_SSC_IER_OVRUN | AT91_SSC_IER_RXBUFF | AT91_SSC_IER_ENDRX);

#ifdef DEBUG_IRQS

sscIrqMask |= set_debug_irqs();

#endif

HAL_WRITE_UINT32(sscState.sscBase+AT91_SSC_IER, sscIrqMask);

#endif

AT91F_SSC_EnableRx(&sscState);

}

Why does the transmitted data appear in any channel, when it should always appear in one.

It appears that the transmit is not waiting for the synch before it starts, or that the PDC is too slow

to reload, even though it has two buffers of 25mS each.

The receive data likewise appears in and accross random channels, again as if the synch is not being honoured.

So, obviously I have something wrong with the setup of the synch start condition.

But, i have tried every combination, to no avail.

Dave