Hi, I am designing a multiple stage amplifier. I have a first stage differential amplifier using JFETs which gives output with a 5 volt offset on the drain. Now i want to amplify this signal more, i can't feed it to the intrumentation amplifier without blocking capacitors. And i want to avoid using blocking capacitors. For this reason i was thinking to design another differential stage using PNP BJTs to amplify as well as DC level shift the signal to 0 volts. Then if needed i can feed this to a instrumentation amplifier. So currently, i am trying to design a PNP differential stage which can take 5 volts as the base and collector around 0 volts. I have tried some simulations in spice but can't get it working. Can anyone help , please?
Differential amplifier offset issue
Oct 10, 2006
2 Replies
The simplest way is to use two resistors, say 50K and 150K in series to
-15 volts.
The center tap will be at zero volts.
You lose a little gain but what the heck.
or use a 5V zener in place of the 50K resistor, no gain lost.
The best place to eliminate the offset, is probably the first stage. How about showing us what you have, so far, as a first stage. If you are using LTspice to simulate, you can post a copy of the schematic file. Otherwise, point us to a web page where the schematic is available, or post a graphic in alt.binaries.schematics.electronic.
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