differential input amplifier

Mar 18, 2007 3 Replies
T

Hi All I am a bit confused with the differential input amplifier concept, I hope experts out there can give me some assistant.



For the differential input amplifier to achieve the max dc gain, does the Vin- and Vin+'s dc voltage must be zero? I uses the netlist below for implementing my 2 stage amplifier, it seems that both Vin- and Vin+ equals to 0V gives me the highest dc gain (64dB)



If Vin- and Vin+ all equals to zero, does that mean there is no input- offset voltage?



Finally, I am just wondering, does the max and min output voltage of the 2 stage amplifier depend only on VDD and Vss values respectively? I simulated the .dc response and the plot shows that the max output voltage is 2.5V and the min is -2.5V which are VDD and Vss. So, do VDD and Vss control the output voltage or is it just a coincident?



I would be really appreciate if someone could clarify my questions above.



Thanks


*Netlist: VDD 1 0 DC 2.5 Vss 7 0 DC -2.5 VbiasQ5 2 0 DC 1.5
  • Mp5 8 2 1 1 p1 W=200u L=1.2u

+AD=840p AS=840P PD=210u PS=210u Mp1 10 9 8 1 p1 W=200u L=1.2u
+AD=840p AS=840P PD=210u PS=210u Mp2 12 11 8 1 p1 W=200u L=1.2u
+AD=840p AS=840P PD=210u PS=210u Mn3 10 10 7 7 n1 W=100u L=1.2u
+AD=420p AS=420P PD=110u PS=110u Mn4 12 10 7 7 n1 W=100u L=1.2u
+AD=420p AS=420P PD=110u PS=110u Mp6 13 2 1 1 p1 W=200u L=1.2u
+AD=840p AS=840P PD=210u PS=210u Mn7 13 12 7 7 n1 W=200u L=1.2u
+AD=840p AS=840P PD=210u PS=210u CL 13 0 .5PF
  • simple compensation network

*Cc 15 13 ?? pF
*Rc 12 15 1
  • VINL 9 0 dc 0 VINH 11 0 dc 0 ac 1

*
*.op .dc Vinh -2.5 2.5 .0001
*.ac dec 20 1 1G
*.TRAN 0.001m 20m .TEMP 27.0
*
  • Microwind 0.6 micron foundry level 3 models

*n-mos model .MODEL N1 NMOS LEVEL=3 VTO=0.80 U0=600 TOX=15.0E-9
+LD =0.010U THETA=0.200 GAMMA=0.700
+PHI=0.700 KAPPA=0.010 VMAX=130.00K
+CGSO=100.0p CGDO=100.0p
+CGBO= 60.0p CJSW=240.0p
*p-mos model .MODEL P1 PMOS LEVEL=3 VTO=-0.80 U0=200 TOX=15.0E-9
+LD =-0.050U THETA=0.200 GAMMA=0.450
+PHI=0.700 KAPPA=0.040 VMAX=100.00K
+CGSO=100.0p CGDO=100.0p
+CGBO= 60.0p CJSW=240.0p .END
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D

[snip]

I'm sorry..I had to stop reading there..I was hurting myself... :) Anyways...I'm no expect but I'll give it a go... Ideal differential amplifiers work by doing Gain* (Signal A - Signal B) The gain (AC and DC) of a differential amplifier is determined by the components used and any feedback loops. The signals on the inputs are ideally not to affect the gain. Make a diff amp signals equal (within limits) and what remains is the offset voltage.. The offset voltage gets amplified too. D from BC

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T

So if I have both inputs equal to zero, should my offset voltage also equals to zero?

Thanks

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D

The offset voltage can be nulled out so that 0 volts on each input yields 0volts out. Often this can be seen on op amp datasheets. Low offset diff amps are often desired. Spice models sometimes use Vos= 0. The offset voltage is due to mismatches inside the op amp. Vos is a concern when it's amplified so much that dynamic range suffers, there can be clipping and there's a coupling annoyance for those that don't like DC blocking capacitors.

Read about offset current too. D from BC

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