Differential amplifier with DC offset

snipped-for-privacy@gmail.com schrieb:

Use a constant current source from the FETs common source point to the negative supply( hope it exists ). Each side will drive half the current of the current source (Icc) with delta_Vin=0. The drain resistors should have a value of R= V+/Icc. This leads to a voltage drop across the drain resistors of about Vcc, so you'll get an output voltage of (nearly) 0V.

Hope it helps - Udo

Udo Piechottka schrieb:

Sorry, R=V+/(Icc/2)

thanks Udo, I understand that part. I think i didn't explain my setup properly. I have a first stage differential amplifier using JFETs which gives output with a 5 volt offset. Now i want to amplify this signal more, i can't feed it to the intrumentation amplifier without blocking capacitors. For this reason i was thinking to design another differential stage using PNP BJTs to amplify as well as DC level shift the signal to 0 volts. Then if needed i can feed this to a instrumentation amplifier. So currently, i am trying to design a PNP differential stage which can take 5 volts as the base and collector around 0 volts.

snipped-for-privacy@gmail.com schrieb:

The problem stays the same.

You'll raise the total error with each additional stage.

So if you are planning to use an instrumentation amplifier the amp will glad to see the differential voltage from your first stage. To increase the gain select the appropriate amp.

What about the power supply? Please desribe what you are intended to realize...(schematics?)

Udo

Is it a constant offset though or does it vary with temperature etc