Debouncing....at About 1Mhz

D from BC · 2007-11-01T05:53:15+00:00

This has got to be a classic signal clean up problem....I need a circuit that triggers on edge A, then ignores about 0.1uS ofjitter then triggers on edge B and then ignores a following 0.1uS ofjitter. +-+ +-+ +----------------+ +-+ +-+In | | | | | | | | | | A | | | | B | | | |-------+ +-+ +-+ +-+ +-+ +----------- || || | | Out +------------------------+ | | A' B'-------+ +------------- Edge A to A' is ~ less than 10nSEdge B to B' is ~ less than 10nSAll values are approximates."In" and "Out" are repeating waveforms.I think I can do it with:1 flip flop 1 >0.1us delay circuitSprinkled with gates..Or maybe I need 2 flip flops..one for edge A and one for edge B..I'm not even sure yet which type of FF to get.If anybody has done this problem before and doesn't mind sharing..letme know a topology...In the meantime, I'll be doodling until I get a solution...D from BC

D

D from BC 18 years ago

Wow! You guys seem to be hitting rock bottom in circuit reduction.

I was going back to block diagrams that were turning into some bloated circuits.

I did one drawing with the input waveform driving 4 circuits simultaneously:

1 negative edge triggered one shot (ex. HC123) 1 positive edge triggered one shot 1 Negative edge ff and 1 Positive edge ff. Then tried some convoluted cross clearing between all of the above.. Sprinkled with gates where needed for decoding and to shorten the in/out edge delay.

I think if I boiled down what I got... it would look something like the above (quoted) circuit.

D from BC

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John Fields 18 years ago

Yup, you\'re right. I glossed over the delay chain and didn\'t notice the grounds. But, there\'s an even bigger error in that the output should be Q\\ since what\'s on D will be old data every time clock goes high and what you want as an output is its complement, as Tom Bruhns noted earlier, I believe. There\'s also the question of input-to-output delay, and looking at 74ACXX, the typical prop delays are, for an 86 and a 74, 4.5 and 8.0ns respectively, which doesn\'t quite meet the 10ns spec. Max prop delays are 8.5 and 10ns respectively, which is almost twice the spec. So, it looks like that, without culling, PECL is the way to go. no?

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John Larkin 18 years ago

No.

Modern cmos flipflops have Q and Qbar, so take your pick. They are fast, too.

John

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John Fields 18 years ago

The point isn\'t that they have Q and Qbar, it\'s that you made a mistake by specifying, verbally and graphically, that the output be taken from Q. And yes, they\'re fast, but not fast enough to guarantee an input-to-output delay of

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D from BC 18 years ago

Oh oh...looks like the road gets bumpy around 10nS...

I'd rather get off the logging road and steer back onto the highway with the low speed limit.

I'd go for the best that can be done with the 74X series to start. That

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Tom Bruhns 18 years ago

Just do it in a modern CPLD, and 10nsec should be easy. Though there's a bit of overhead getting started in CPLDs, it's cool that when you make a mistake in your logic or see some improvement, it's just a re-route.

For logic (if you are willing to get away from your SN7474 and SN7486 parts...), you could use LVC parts at 5 volts. They're fast.

Cheers, Tom

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T

Tom Bruhns 18 years ago

Oh, good heavens. Isn't this beat to death yet??

TI 74LVC2G74: max 4.4nsec clock to /Q over temp at 5V+/-0.5V TI 74LVC1G386: max 3.5nsec input to output, same conditions yields max 7.9nsec over temperature. Assumes max 15pF load, which seems reasonable under the circumstances of low fanout.

It is, of course, pretty easy to find parts to do it faster if you really want.

Cheers, Tom

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John Larkin 18 years ago

What the hell is your problem? I suggested a circuit to solve a problem, for free, and someone else, not you, pointed out that the output is inverted. It is: So what? Use Qbar or swipe an xor section and fix it, with my blessings. All you pointed out was that you didn't understand the clock chain.

My ego isn't invested in this, but apparently yours is.

Sure, several. FACT is decades old.

John

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John Larkin 18 years ago

If you can tolerate edge delay, just lowpass the input (rc or rlc) and run it through a schmitt gate.

Where is this horrible signal coming from?

John

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John Fields 18 years ago

Really? I readily admitted that I made a mistake by glossing over the clock chain, but you seem to be getting hot under the collar for having been called to account for committing the same sort (one would hope) of error regarding the direction of the output.

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John Larkin 18 years ago

I'm not hot, and you can't "call me to account" because I don't answer to you. If you want to keep your private score, go for it.

It's not a design, it's a suggestion. It doesn't cost anything and it doesn't come with a warranty.

If you want logic, look at ONsemi, Fairchild, or TI. They have some.

John

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John Fields 18 years ago

Then: "What the hell is your problem?" is your normal tone of voice?

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Ken S. Tucker 18 years ago

I like this family, claims to be 50 Mhz,

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Cheap too, otherwise I won't have a bunch of

74HCTLS175N's in stock! Regards Ken

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D

D from BC 18 years ago

On Fri, 02 Nov 2007 11:03:40 -0700, Tom Bruhns wrote: [snip]

Thanks for the headsup for the future.

Did a quick read on

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:O .ohhhh that looks scary...

Is CPLD work more complicated than programming microcontrollers with assembly?

D from BC

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John Larkin 18 years ago

Somebody makes a tiny-logic cmos flipflop with Tpd of 1 ns. That's as fast as 10KH ecl.

John

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D

D from BC 18 years ago

The signal is off a comparator that's bouncing due to some ring off an inductor.. I'm not making any changes upstream. That's all firm and I've beaten that part to death for the least amount of bounce..

On the matter of posts with circuit errors... I don't mind circuits with errors... Heck..If somebody posts a fortune cookie message, I can probably turn it into a circuit. :) "When you have square mice...Use 4 mouse traps.." ok...I just made that up...but it's slightly relevant to the debounce circuit I'm working on.

I often see the ideas, paths,get the gist or objectives of circuits even if a circuit doesn't work.. When I get circuit ideas it's kinda like a dart board full of darts. One can roughly determine where the target is by all the positions of the darts.

D from BC

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John Larkin 18 years ago

Yup, NC7SV74. But you can get it in the bigger US8 package, which you can practically see with your naked eye. In bright light.

Some of these TinyLogic parts can put almost 5 volts into 50 ohms with a risetime of 600 ps or so.

John

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John Larkin 18 years ago

of

sharing..let

I don't mind if somebody points out an error, or better yet suggests an improvement, or riffs on an idea. This is just play. Some people play whack-a-mole with ideas, pounding them as soon as they pop up.

When we bought our building, it was a working fortune-cookie factory, owned by the Louie family.

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They gave us a couple of big boxes of cookies with the building, and here were the first two I opened:

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Google "Louie Fortune Cookie Machine" for some history.

John

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D from BC 18 years ago

I think I spotted that part while browsing ff's on Digikey. IIRC that part is so small..fleas can use it as a coffee table.

D from BC

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D

D from BC 18 years ago

[snip]

All fortune cookies are so positively biased.

What if people got these in fortune cookies :)

"Leave a big tip for extra luck" "Please check another fortune cookie" "Game piece 27...Get all pieces and win a free fortune cookie" "Only 21 calories!" "For success, do not read this fortune cookie" "Fortune cookie business for sale. Only $44000. Call ***.***" "Get 2x larger see

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" "You've opened our 1millionth fortune cookie!" "Medium size. Wash in luck warm water. No ironing."

D from BC

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