debounce

john larkin · 2026-08-17T21:36:42+00:00

We are making a 4-channel tachometer module. After a bunch of analogstuff, four logic signals run into an FPGA to be processed. The fpgawill use a 50 MHz clock for the tach logic.I used OPA197 opamps as the comparators. Their outputs run through ashort ribbon cable from the analog board to the FPGA board. The edgesare kinda slow, > 1 us, and might pick up noise, so I figure we shoulddebounce them digitally in the FPGA.Suggestions?One could push the signal into a long shift register clocked at 50MHz. All 1's could set a flop and all 0's could clear it. Maybe 32flops long? Clumsy.Or some sort of up/down counter?