Cons of FPGA

It's all about non-recurring costs.

I don't know the current figures, but getting an asic means paying for the device level design and the masks required to turn the design into working silicon, both of which meant spending tends of thousands of dollars up front, which used to mean that you have to expect to be able to sell about 100,000 parts before you could start making money on the lower cost of the part itself.

-- Bill Sloman, Nijmegen

A FPGA is on the route to an asic if the specifications permit. For standard applications this is the case and help you save costs while developping an asic.

Depends entirely what you compare it to in different apps. A CON for one app might be might not be a CON for another application.

Some potential CONs:

- they can use a lot of power

- the packages can be BIG. Higher density forces you to use bigger packages (see my rant:

)

- they can be very expensive (thousands of $$$$ *per chip* for the really high end devices)

- they can require external programming devices (some are built in)

- they can take time to "boot up" (a few are instant-on)

When you have enough money and volume, and/or need lower power, smaller die size etc.

Dave.

It's all about non-recurring cost vs. recurring cost vs. technical features.

ASICs are (or can easily be) smaller, faster, lower power consumption devices with a much lower per-chip price than an FPGA. But the cost and time for getting one made is huge.

FPGAs are big, power hungry, hard to get working fast, resource constrained (you almost never use all of everything you have -- you usually end up not using logic, or memory, or I/O, or something), and expensive on a per-piece basis.

Use vacuum tubes -- it's a proven technology :-).

--

Tim Wescott
Wescott Design Services
http://www.wescottdesign.com

Do you need to implement control loops in software?
"Applied Control Theory for Embedded Systems" was written for you.
See details at http://www.wescottdesign.com/actfes/actfes.html

It is really really hard to make a low noise amplifier with good distortion numbers from an FPGA.

Before you design in an FPGA, CPLD or even a simple PAL, send me an e- mail asking if I have designed it in. If I have don't use it. I am still batting 1000 on every part like that I design in, they quit making.

But seriously, it is all about the engineering time per unit sold.

Also don't write off the idea of using a micro too quickly. If you can make a micro do it, it will likely be cheaper than an FPGA to implement.

Well, I think your homework has been done for you, now.

Jon

FWIW, I stopped using FPGAs in 1997 at the Xilinx XC3064 level.

The tools kept changing, they washed their hands of their older dongles (I had to find a Russian cracker to crack the s/w so I could carry on using the stuff I paid $xxxxx for) and it made sense only if one was working with the tools full-time.

Leave it for a year and the tools have changed and you have more to learn.

The designs are not backward compatible so the only way to run an FPGA product for say 10 years is to dedicate a special PC to the FPGA station and keep the various version of the software on it. And hope the dongles don't break off ;)

And design rules which worked for a few years would stop working once Xilinx made their D-types faster so the D-Q propagation time became shorter than the short-interconnect delay - that broke a lot of my designs and obviously would break any ASIC design because a fundamental assumption of any synchronous design is that the interconnect has less delay than the logic.

It just became a huge hassle to maintain the capability.

Obviously hard logic is the only way to do a lot of stuff but I would try using a fast microcontroller, perhaps with a bit of external logic, if possible. The assembler for it can run in a DOS box of any OS and the design is easy to revisit after x years.

But then I am in industrial electronics and run products for 15 years

+.

Interesting, but these days tools are usually free from the vendor, except support for the largest parts. Dongles are pretty rare these days, I think you can get dongles for Altera tools, but there are other solutions too, like floating licenses or locking to particular computer, MAC address or HD number or some such.

There were other problems too in the old days, like the myriad of HDLs. I had to port some Lattice CPLDs to current devices a few years ago. One was done in Abel, which is no problem, but the other two were in "LHDL", Lattice's proprietary language. Good thing they had a knowledgeable FAE...

But isn't one use for programmable logic in industrial electronics implementing old chip functionality inside FPGAs, when those things go out of production or can't otherwise be used? Especially for products that have to last longer than 15 years... I did that kind of project once, implemented some really weird old Siemens 2 Mbps switch chip and put a good old 8259 in there too.

Anssi Saari wrote

Xilinx used to charge $thousands for the routing stuff (XACT 6) but the schematic entry stuff (Viewlogic 4 in those days) was pricey too. I've still got all that stuff, in boxes somewhere.

One customer came back a year back for a re-order but luckily I found some of the XC3064s somewhere and used the original hex file.

Yeah, really great. An even better way to get screwed.

I gather than most FPGA designs moved to VHDL type tools in recent years. Again, they were pricey, unless you went for the bottom end. I recall doing a really weird design flow once: it was a horrid state machine which I did in CUPL, then used some Viewlogic tool to synthesise the schematic from the logic equations, then merged this into the rest of the design. In VHDL, this would all just come together. But what a learning curve.

Sure, that's one app. But these are big jobs. I once spent a year on one design.

It's an interesting way to make a living as a consultant, but when in manufacturing one avoids dead end technologies, which FPGAs are - not because the chips become unavailable (you can still buy an XC3064) but because the tools are so hard to learn and to maintain.

On a sunny day (Fri, 17 Apr 2009 13:47:35 +0100) it happened Peter wrote in :

Xilinx has clearly stated in comp.arch.fpga that the 'webpack' is not intended for professional use. That was obvious to me the first time I used that... You are absolutely right. ('webpack' is the free Xilinx software', at least last time I looked). OTOH I found the Altera free software of a lot better quality. Competition is good. It likely will be Verilog and / or VHDL these days that one uses. In many cases things can be done faster, simpler and at lower cost with some micro. When requirements are very high speed, or lots of glue logic and I/O, or both, FPGA can reduce chip count a lot, also for high speed signal processing, like video codecs.

Your fundamental assumption amazes me. I have only done 1 project with FPGAs (polar format variable pixel rate video controller and dual-port video memory DMA controller for a RADAR target generator), but knowing how clueless I was on the subject I hired a mainframe ASIC logic designer to teach me how to do rigorous synchronous state machine design. Rule one was *never* use single rank transparent latches, because race conditions can occur if signal propogation around the loop is faster than the latch transparent time, and parts/processes are constantly getting faster. With dual rank latches and a two phase clock there is *no* dependency on minimum propogation delays. The "D-Q propogation time" through the two latch ranks includes the minimum time between first and second clock phases; which can be (usually is?) different from the time between the second clock phase and the first (allowing longer time for propogation of async gates than sync latches, as required by your worst case timing analysis.)

Until your post I never suspected that anyone did it any other way.

I grew up on toooooobz - when they invented the transistor, it took me awhile to wrap my head around how they worked; then along came the JFET and I was, like, "Hallelulah! A transistor that acts like a toob!" ;-)

Cheers! Rich

Yeah, and all those $49 programmers for microcontrollers to get engineers "started" aren't intended for production use either, since they don't actually test memory retention at the extremes of VCC, right? :-)

I haven't done FPGAs in something pushing five years now, but when I did, I always found Altera's software to be rather lesser-featured than Xilinx's, but the quality of both was pretty good.

---Joel

On a sunny day (Fri, 17 Apr 2009 10:28:47 -0700) it happened "Joel Koltner" wrote in :

Well, that is true, but that is hardware. I dunno about mplab, as PIC user I use gpasm exclusively, and my own prog software. Having written own programmer makes it so much easier to adapt to some new PIC. And i can blame myself if something goes wrong (happened some times).

Well I could rant about xst (webpack) for hours, I will spare you that, but in my view, as programmer, it is a kids stuff all done the wrong way basis with loads of stuff build on top of it. It has cost me days of time, gives error messages that have no relevance to the problem, causing you to look in completely the wrong place for what is wrong, it should be burned. At least it was that way, indeed I have not used it for some years, it could be worse now :-)

Websack has this incredible learning curve, and what you actually learn is how to navigate around its bugs, something that Altera did not have, when I used their soft it was like a ten ton load falling of your shoulders. There is a nice Verilog compiler too, 'iverilog', I used that to actually write and test the HDL, before trying to synthesise anything in wepsack.

Glen Walpert wrote

I think if you look at schematics of standard 74HC type logic, where there is just one clock, or look in any textbook which shows schematics of shift registers, counters, etc, they all use just the one common clock line, and obviously they all rely on the D-Q propagation time being longer than any timing skew on the clock wire. This is how people have been building logic for far more years than I have, AFAIK...

With most logic, one doesn't have the luxury of a 2 phase clock. In an FPGA you can do all kinds of things...

But as D-Q has gotten faster, clock skew has also dropped. Clock trees are pretty impressive these days. I've never seen a fast-mode (set up) timing problem in a properly designed circuit. I saw it in LSSD ASIC designs (two phase clocks with transparent latches), but it was always checked.

Because you can make horrid designs doesn't mean you should.

In 1999 the Xilinx Alliance place and route tools were about $1000. I was using Synplify for synthesis because the Xilinx' stuff sucked. The free stuff is much better now.

How so? MACs can be spoofed too.

It's all pretty much free now, except the very high end parts. I suppose the idea is that if you can afford $5K-$10K parts you can afford the tools to go with them. ;-)

Actel comes with Synplify and ModelSim. The FAE told me the other day that other than being the slow version, ModelSim isn't crippled (10K line limit) as the Xilinx and Altera versions are.

A year isn't really a very long time.

I guess if you avoid some problems you can ignore some solutions.

in an FPGA it's all build in, the hold time on the flops is practically zero with clock skew is taken into account, so static time analysis just works when you do a nice synchronous design. You only have to make sure the delay from flop to flop is less than the clock cycle plus setup time.

you don't need that, run everything on the same clock and all you need to know is that the logic delay between flops is shorter than the clock period.

-Lasse

74HC is edge triggered, not transparent, so a two phase clock is not a necessity there. I misinterpreted your issue, associating a D-Q propogation time as a property of transparent latches only, and Clk-Q time the propogation delay of interest for edge triggered latches. Clk-Q propogation time being faster than clock skew is a problem only if a fast Q out gets to another D input before it gets its clock (+/- hold requirement), which sounds like something that might happen if there are no gates in that signal path, which could be avoided (e.g. two inverters flagged not to be optimized out) without resorting to a 2 phase clock IMO although a 2 phase clock could also solve that problem.