I usually drive relays with a logic-level mosfet, like FDV301. Lots of relays, we use a TPIC6595, 8-channel SPI driver, which doesn't need diodes.
-- John Larkin Highland Technology, Inc picosecond timing laser drivers and controllers jlarkin att highlandtechnology dott com http://www.highlandtechnology.com
I'm a little confused. What does polyphase filtering have to do with linear or other means of interpolation? I have designed polyphase filters which have to do with sample rate conversion and elimination of unneeded operations. It is an implementation technique rather than an algorithm or equation that will interpolate. Linear interpolation is an algorithm to interpolate. What is the filter you would use the polyphase technique to implement?
I find it funny that Larkin would rather poke fun at old transistors than to discuss the topic where he might learn something.
-- Rick
Am 06.12.2014 um 20:02 schrieb John Larkin:
Use my VHDL sin/cos function on opencores. Just connect the phase in / amplitude out busses and the module will determine the required table sizes and compute the tables at compile time, everything nicely rounded to the closest precise value. Requires VHDL only, no extra tools.
<Part of the motivation for this was that the Xilinx tables had a range from +128 to -127 for an 8 bit output which created a DC offset in a phase demodulator, and it also silently changed the pipeline delays depending on speed requirements. That is funny if you want to align your symbols to the carrier.
And for something that simple, I would never again lock myself to one chip vendor.
Gerhard
I'll tell my FPGA droids about the opencores thing. Thanks.
We'll probably go 16 bits on 8 channels, at 2 MHz, so we might elect to timeshare one sine table.
-- John Larkin Highland Technology, Inc picosecond timing laser drivers and controllers jlarkin att highlandtechnology dott com http://www.highlandtechnology.com
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They spend lots of effort optimizing it knowing all the tricks and details of the internal workings of the FPGA
smaller so you can fit more stuff next to it, faster so you don't have to buy a faster FPGA if you are pushing the limit
encrypted block, but so it really everything goes on inside an FPGA none of them are open
sure but we generally don't go out and mine our own copper ore
your 16 bits, 8 channels DDS with a shared table is literally a 2 minute jo b
and then you can go on to design the complicated stuff the guy next door ca n't
-Lasse
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