Current State of ASIC, do or dont

Nice. Can you remember what the price was for the component when packaged?

Cheers

Klaus

IIRC ~$30 each, but this was for a fairly low quantity sonar application... commercial fishing... a couple of wafers yielded a years' supply ;-) ...Jim Thompson

We have different definition of NRE. You

Wrong. My NRE included design, layout, masks, one process run, 25 samples. Read above, $200K-$140K design cost leaves $60K for masks and a prototype run (Todd James did the layout as well as the digital core).

If you've been going to the big name standard parts houses for your custom work, you've been screwed... they have large overhead costs, ridiculous software costs, Obamacare, expensive CEO's, etc >:-}

We freelancers don't have those costs... and we deal direct with foundries that specialize in custom runs... including some new possibilities in mainland China. ...Jim Thompson

"Jim Thompson" wrote in message news: snipped-for-privacy@4ax.com...

So the cost of *a* mask is essentially constant, and the big expense is needing a ton of them for e.g. many process steps, extra metal layers, etc...?

I suppose I'd still expect something like a freaking desktop CPU to cost more, because there's just *so damn much* on them (bigger masks?..or are all masks truly the same size?). But that's orders of magnitude beyond the scope we're talking here.

Tim

I talked to a design house last year, they named a price for the wafer and obviously according to the size of the die, the price of the final production part correlates to the complexity.

But, base cost like package, test and logistics add to that. In the example we had, the cost of each of these was as high as the cost of the silicon

Cheers

Klaus

Pretty much so... some of the chips I've done have a 20-mask "stack".

There's E-beam masking going on, but I don't know the extent of it. ...Jim Thompson

Quite often packaging and testing far exceed the die cost.

That's why so many consumer-level products use chip-on-board... chip mounted directly to a PCB, wire-bonded or clips or face-down, then "glopped" with a protective coating. ...Jim Thompson

Wow. I've never made it past 11 masks. But I am younger than you :-)

When I left IBM in 2006, our cost for a set of PPC-970 (Apple G5) masks was just over $2M. The costs of masks is *not* a constant. It's hichly dependent on chip size, number of layers, and most importantly, feature size.

I have a lot of designs that have 1.5V and/or 1.8V and/or 2.5V digital cores, then 3.3V or 5V analog, plus maybe a 30V output stage, add hi-value Ohms/square poly resistors, etc, etc. ...Jim Thompson

My current one is MEMS, base wafer with all kinds of metallizations and oxides, then an SOI with more of those. So technically this has more layers but it doesn't count because the SOI would count as a separate wafer in a "who's got the most masks" contest. The two get married in your neck of the woods.

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MEMS and analog chip doesn't care much about process geometry, but the digi tal side does, and cost goes exponential with smaller geometry. So, we hav e the digital chip bonded to the analog chip and call it mixed signal. We can put more NRE into the digital side to lower chip cost, but the limiting factor is still in the analog side.

I really never thought about that

Isn't the reliability bad for that solution, the package will relieve thermal expansion stresses?

Cheers

Klaus

No difference from mounting on metal frame. Gold wires are flexible enough for thermal stresses

The only reason a package reduces stress is the moly tab the die is bonded to. With chip-on-board, you're usually dealing with low dissipation situations and the bonding material is a electrically conductive epoxy. ...Jim Thompson

Ok. And the reason why it is not used more often for commercial/industrial products, is probably because on the package is saved from the equation?

Cheers

Klaus

GM is noted for building their engine controller systems on thick alumina, and doing chip-on-board. ...Jim Thompson