Current State of ASIC, do or dont

Hi

We have a very high volume circuit, used in several product, about 1mill pcs per year. Another more complex circuit go at 100k pcs per year

The circuit is a mix of digital functions, small signal transistors, some high voltage stuff (< 30V) and PWM controllers for SMPS

I need some input to how the ASIC marked is today:

  1. NRE costs
  2. What is relevant to implement into an ASIC
  3. Cost per ASIC (really, if it really is relevant to go down that path)
  4. Cost of number of pins for the ASIC, package costs

We have ASIC experience inhouse, from 10 years ago, but I want to know the current state of art

Thanks

Klaus

Reply to
Klaus Kragelund
Loading thread data ...

Depends completely on the circuit complexity _and_ its voltage(s)

Packaging is often more expensive than the chip itself.

Contact me directly, get an NDA in place, then I can tell you reliable numbers. ...Jim Thompson

--
| James E.Thompson                                 |    mens     | 
| Analog Innovations                               |     et      | 
 Click to see the full signature
Reply to
Jim Thompson

What's your reasoning for moving to an ASIC? Cost, packaging, reliability, etc.? Are the devices containing it/them considered disposable? Or, will you make spares available for depot repairs, etc.? (what are the consequences of some constituent component failing and rendering the entire device useless?)

Are the digital functions simple? Or complex? I.e., embedding an MCU in a mixed mode ASIC is different than building some flip flops. Do you own (or develop) all of the IP? Or, are you licensing any of it from third parties?

Packaging costs tend to be "surprising" -- esp with mixed mode where you might have something switching (relatively) heavy currents "here" alongside a digital core running on a volt or two "there". Temperature differentials across the package, etc.

What do "local" foundries houses tell you?

Reply to
Don Y

l pcs

y,

Cost is the driving factor. I expect the ASIC to have minimum the same reli ability as the discrete parts/ICs.

ences

The device is part of a product. If they fail, the entire product is failed and either thrown out or returned to the manufacturer for recycling

me

It is simple, in one case just a replacement for an IO extender. In another one, we could insert a PWM controller functionality, to remove that part f rom the design. Other part is standard grade opamps, multiplexer, glue logi c, linear regulators, diodes etc.

We own the entire IP

ASIC

er of

de

ls

If the design gets to complex (expensive), we can revert back to only singl e mode (no mixed mode)

the

I have not contaced any. Need some pre-knowledge to ask the right questions . Any books out there on ASIC and practical tips/tricks?

Cheers

Klaus

Reply to
Klaus Kragelund

ill pcs

ity,

liability as the discrete parts/ICs.

quences

ed and either thrown out or returned to the manufacturer for recycling

some

er one, we could insert a PWM controller functionality, to remove that part from the design. Other part is standard grade opamps, multiplexer, glue lo gic, linear regulators, diodes etc.

r ASIC

mber of

u

side

ials

gle mode (no mixed mode)

The main determination factor is pin counts and thus package size. What is your estimated pin count?

w the

ns. Any books out there on ASIC and practical tips/tricks?

Any one doing ASIC is probably too busy writing books. Ball park number of NRE is $200K and +/- $1 per chip. But of course, it depends.

Reply to
edward.ming.lee
[snip]

Somewhere between 32 and 64 pins

Ok, that is good first info :-)

Cheers

Klaus

Reply to
Klaus Kragelund

Naaaah! NRE can be anywhere from $50K on up... depends on complexity, and voltage(s).

Finished part costs are mostly pin count related, but heavy-duty testing can drive the cost way up (we smart designers use BIST :-)

Most of my chip designs are 6-28 pins and are in the < 25 cent range.

Complex packages can add $$ to the individual part cost.

A circuit designer's knowledge of layout techniques and proper annotation of the schematic as to matching, metalization routing, etc, can shave $$ off of the mask designer cost, see...

...Jim Thompson

--
| James E.Thompson                                 |    mens     | 
| Analog Innovations                               |     et      | 
 Click to see the full signature
Reply to
Jim Thompson

I meant too busy making money than writing books.

Yes, he needs fairly high voltage mixed signals. Up to 200K is more reasonable.

He said 32 to 64 pins; so, more expensive than your chips.

Reply to
edward.ming.lee

Perhaps. Those not in the biz ought to refrain from pontificating.

I've designed _hundreds_ of working chips. ...Jim Thompson

--
| James E.Thompson                                 |    mens     | 
| Analog Innovations                               |     et      | 
 Click to see the full signature
Reply to
Jim Thompson

Jim, I will contact you offline

Cheers

Klaus

Reply to
Klaus Kragelund

It'll usually be higher. Lower parts count, less things to break.

[...]

I am in no way an IC expert like Jim but the few ICs I've helped design were all mixed mode. It is no problem at all. Where it was tough in our cases was where we needed high voltage extensions in a process which adds a lot of cost and reduces the selection of fabs greatly.

I learned the stuff with an older book from the 90's and it still appears current when looking at today's mixed signal designs. It is Geiger, Allen, Strader "VLSI Design Techniques for Analog and Digital Circuits", McGraw Hill. It helped me in finding what can be done and what I better not do when designed at the transistor level.

When you transfer a discrete design to ASIC some circuit architectures may have to change. For example, IC processes are very bad in terms of absolute calues of resistors, can't have any large capacitors (gets expensive) but ratio accuracy is much better than discrete.

Can't comment on the cost topic because the few ASICs I've been involved in were cutting edge high-density (very small form factor) ones, pushing design rules hard, and that's not typical. NRE was usually between $150k and $500k and the parts single digit Dollars or less. But always unpackaged in our case and as was said packaging and testing add a lot of cost per device.

ASIC opens whole new avenues and ideas for miniaturization that you don't have with discrete. Here is an example of what that can do:

formatting link

Without ASIC technology this product could not exist.

--
Regards, Joerg 

http://www.analogconsultants.com/
Reply to
Joerg

Nice, I'll check that one out :-)

Yes, I knew that much, it also is hidden in the fineprint for example for the IC's with internal PGAs, often they are off when the values of resistances get different, for higher gain

That is a really nice, incredible high density :-)

Cheers

Klaus

Reply to
Klaus Kragelund
[...]

Mounting is the tough part. Semiconductor equipment manufacturers we contacted responded with comments like "That cannot be done", "Impossible" or "You guys must be out of your minds". Meaning we essentially designed the assembly machinery ourselves. Mass production of the device began in the 90's and it's still going.

--
Regards, Joerg 

http://www.analogconsultants.com/
Reply to
Joerg

I think that depends on the sort of "mix" that you expect in that package. But, as you are treating the entire product as "disposable" (see below) you could engineer for the required level of reliability (disposability?? :> )

OK. In my case, I was trying to put an SoC core, PoE/PoE+ PD controller and 2x10/1x20W class D amplifier in the same package. My initial research indicated that this was far too diverse a mix for an "efficient" design. Even if I replaced the SoC with my own custom core (losing flexibility in the process) and moved to CoC packaging for some of the run-of-the-mill components that could be "externalized", it was just not worth the effort (unless I wanted to go into business *selling* the things myself -- not high on my list of "how to waste years of my life"!)

And, when you added the rest of the components that *couldn't* be part of the device (connectors, heat sinks, power conditioning, etc.) it didn't make much overall difference (e.g., my "all COTS" solution is probably 50% larger, probably draws just as much power for per equivalent function and maybe costs 2-3X)

I'll let someone else (i.e., interested in wasting their life SELLING!) make *that* investment.

OTOH, it showed me that pure digital designs are quite affordable and so I'm pursuing other devices that are less taxing on the "process".

OK.

From what you described, you can probably adapt the digital stuff to whatever process rules the *analog* requires of you.

I haven't read anything on the subject in many years. Meade/Conway many decades ago, etc. Most of my interest has been in digital devices (where I can put flexibility in *code* instead of poly layers)

Good luck!

Reply to
Don Y

I agree with your estimate. Of course, someone can low ball with 50K NRE, and "make it up" later. 50K just won't go very far these day.

Reply to
edward.ming.lee

Can you tell us how many chips you've designed? ...Jim Thompson

--
| James E.Thompson                                 |    mens     | 
| Analog Innovations                               |     et      | 
 Click to see the full signature
Reply to
Jim Thompson

I uses chips and i can't get ASIC chips for 50K. You can of course. Just not the rest of us.

Reply to
edward.ming.lee

If you are spending so much on NRE it's because your management think that they need to go to the big expensive guys to get a chip made. You don't.

Your management probably also think that to design a chip takes expensive tools ($100K+ annual maintenance per "seat") like Cadence, Mentor graphics, etc. BS! I've designed hundreds of chips using PSpice which cost me all of $8K. Except for its klutzy user interface I'm sure I could design a chip using LTspice... in fact several of my customers use LTspice to verify that my designs meet their specifications.

The "rest of us" just need to use their head while shopping design houses.

Also, I often work hand-in-hand with my customers helping them do their own chip design. ...Jim Thompson

--
| James E.Thompson                                 |    mens     | 
| Analog Innovations                               |     et      | 
 Click to see the full signature
Reply to
Jim Thompson

Even if you work for free. Mask sets cost money. Growing wafers take time and money. I am not saying it cannot be done for 50K. But for 32 to 64 pins mixed signal chip, that would be pushing it.

Reply to
edward.ming.lee

Most analog/mixed-signal chips aren't that many pins. Even if they are, like my billboard LED drivers, they're repetitive cells, so inexpensive _circuit_ design costs.

Mask set cost is _not_ a direct function of pin count _or_ chip size. A mask set cares less how _big_ the chip is. All chip size affects is die/wafer, thus cost per die. (A big, non-repetitive design, may increase the cost of the layout guy... time... but not the mask set cost.)

What _does_ affect mask set cost is _number_of_processing_layers_. Adding multiple voltage capabilities (voltages >5V, or multiple element types, say 1.8V, 2.5V, 3.3V, 5V) increases the number of masks, thus mask set cost.

"Growing wafers takes time and money"... methinks we have an pompous amateur here trying to pose as an expert... probably a kid still in school >:-} ...Jim Thompson

--
| James E.Thompson                                 |    mens     | 
| Analog Innovations                               |     et      | 
 Click to see the full signature
Reply to
Jim Thompson

ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.