cPLDs and FPGAs we've known and loved (or hated)

Are there any FPGAs or even CPLDs currently produced in 40 pin DIL?

I used Lattice isPLSIs (mostly little 1016Es) for many years, but these days it's mostly Actel flash- based FPGAs, ProAsic and A3Ps. I like anything that comes with a free development system, that doesn't need much fancy programming hardware, that doesn't need too many different Vccs, that is available in a QFP package, that is available easily in small quantities, and that stays in production. Which is how I learned never to use anything by Philips.

Almost no useful/interesting parts these days have second sources.

Atmel ATF2500 - not sure if still in production though

But you can write portable VHDL code, which makes it easier to use other devices. In the midrange product lines of Xilinx and Altera there are very similar features, like dual-port block RAM, PLLs, hardware multiplier etc. If you encapsulate the device dependant parts in their own VHDL entities, switching to the parts of the other company is easy, if they don't deliver it any more. But changing the layout and the power supply may be some more work.

OK, I first used that part about 17 years ago, bought a few hundred. Low power, very nice. DigiKey has 708 of the 20ns 40-pin DIP version in stock, $7.55 each, and even more of the 44-pin PLCC types. Mouser has 815 of the DIPs, same price. Both are RoHS Compliant. That part is still moving nicely.

The power supply might be changed with resistor divider. Changing pinout layout is worse.

• free dev system * simple programmer * simple power * QFP/PQ * proto qty

Certainly a plus for any chip manufacturer.

Un bel giorno Frank Buss digitò:

Mostly Xilinx. On occasions, Actel.

I'm considering to switch from X to A from a while. For "historic" reasons I'm bound to Xilinx, but it's becoming too difficult (or I might say exhausting) to get their new devices. Probably a drastic change would still cost me less than to stay with X.

I'm using VHDL. My latest hobby project was a DDS signal generator with CORDIC for sine output and a cellular automaton for the random generator, tested on a Spartan starter kit:

The problem with the fixed clock is high jitter, if the output frequency is near the clock frequency and if you tune it to e.g. 10.000001 MHz and the clock is 50 MHz, it output jumps every second instead of a smooth tuning.

Following some links from your homepage I've found this nice synthesizer:

Using the Analog Devices DDS chip sounds like a good idea. When I have some time I'll try to use it to generate the clock for the rest of my generator, which will allow better fine-tuning of the output frequency and reduces the jitter.

But back to your questions: I've helped a client to develop some VHDL programs for Cyclone (I and II). Usually I'm drawing some timing diagrams and flowcharts, then I implement it in VHDL and sometime writing some testbenches or using the simulator.

I hope I have convinced the teammates to use the simulator more often, because it can safe time. One example: There is a project which needs some

I'm trying some new ideas with VHDL, too. Usually you write multiple processes to implement a design. Last time I implemented a SPI interface I've used the "single-process-method" by Mike Treseler:

It makes the source code more readable, because you don't need to add some artificial synchronizations between the processes and todays synthesizers optimizes it very good.

An extension board I helped to develop uses the Cyclone II. We have used the NIOS soft processor for it and it is very promising: You can just click together your system-on-a-chip, including many ready to use IP cores and it is easy to integrate your own VHDL code (with an IO ports interface and interrupts) and for the small application for which we needed it, the on-chip BRAM was sufficient. The only drawback is the slow recompile time with Eclipse (maybe because it uses Cygwin for Windows, which is not very fast) and some bugs in the tools (there were even bugs in the soft processor and I can remember a bug in Quartus (not NIOS related), which generated wrong state machines. Installing the service pack didn't help, but there was a hot-fix, which patched the service pack, and this solved the problem).

PS: You should ask this in the comp.arch.fpga newsgroup, which is very active with many FPGA and CPLD users.

Now if i could pick up a datasheet from Amtel's website.

Thanks. That size might be useful for me.