The dividers and the phase detector of my experimental frequency synthesizer are implemented in a 15ns Altera MAX7000S CPLD. I've tried different multiplication factors (kN) to see how the close-in phase noise varies. At a 1 KHz offset, I get:
-82 dBc/Hz for N=198 (VCO=19.8 MHz, comparison freq = 100 KHz)
-95 dBc/Hz for N=39 (VCO=19.5 MHz, comparison freq = 500 KHz)
Calculating the equivalent phase noise at the PFD:
-82-20*log10(198) = -128 dBc/Hz
-95-20*log10(39) = -127 dBc/Hz
Given the 5:1 ratio of comparison frequencies, at a guess, I'd expect these to differ by 13 dB if the noise was mainly due to a fixed amount of time jitter at the PFD.
I'm using a 10 MHz canned crystal oscillator, which I'm dividing down (inside the CPLD) to obtain the reference frequencies. I've read these are good for at least -130 dBc/Hz (before dividing down) so I'm a bit dissappointed with my noise levels. Maybe it got a bit too hot when I soldered it to the ground plane! I must try another....
Googling for "altera cpld jitter" doesn't turn-up much, and they don't mention jitter in the datasheet. Does anyone know what sort of performance can be expected from a CPLD in this regard? I don't know if the CPLD, or my circuit lash-up is the root cause.
A full write-up of the project can be found at
It has a fractional-N capability, but noise-levels are the same in integer-N mode with the external RAM disabled.