cmos technology-gate length- power

hi, as the gate length is reduced by going to newer technology why do we need to reduce the supply voltage? one thing is the switching power =alpha*c*v^2*f.by reducing v we can reduce power.but by reducing v we need to reduce the vt also to meet performance.which increases the leakage current.thus by reducing v the dynamic power is reduced but static power is increased.so y do we need to reduce v at all or is there any other requirement that we should reduce v once we have shorter gate length.

Rgds, Sreenath.

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Sreenath
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