Protecting a CMOS gate input

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I'm going to use a CMOS bistable chip (not a uP) that's to be  
manually triggered from time to time by a mechanical switch. It  
has a debouncing circuit but since the switch is to be connected  
by a removable jack-and-cable set and operated by non-techno  
savvy users, I thought I'd include a few extra components as a  
precaution.

The input will have a series resistor followed by a capacitor to  
ground and schottky diodes to Vdd and Vss. Do you think any of  
this is superfluous since the chip already has similar protection  
built-in?

Re: Protecting a CMOS gate input
On Friday, May 15, 2020 at 6:54:08 AM UTC-4, Pimpom wrote:
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If you are connecting this to the external world nothing is superfluous.  You might add a front end bipolar transistor, a zener diode or TVS or maybe even a gas discharge tube depending on the environment.  

I'm curious about what a "CMOS bistable chip" is exactly.  I assume you are not talking about an SR FF?  If so, you don't really need debouncing.  Why use CMOS rather than something more static resistant like relays or fluidics?  

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  Rick C.

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Re: Protecting a CMOS gate input
On 5/15/2020 4:37 PM, Ricky C wrote:
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It's a good old 4013. I used one in a similar sub-circuit years  
ago but in a completely different product. I used a BJT front end  
which also served as an inverter. The present design works  
correctly without inversion so I thought I'd do away with the BJT.

I did consider using a relay but it would take up too much PCB  
real estate. I have a very limited choice of relay types I can  
get. Same with the external switch. I can use only an SPST type,  
so an S-R FF is out.

Re: Protecting a CMOS gate input
On Friday, May 15, 2020 at 7:35:54 AM UTC-4, Pimpom wrote:
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Huh?  Is the FF only to debounce your PB?  What puts your CMOS chip in the other state?  I'm not following what you are doing at all.  I was thinking the PB would connect to one input of the SR and the other input would be the input that resets it.  

I wasn't really serious about the relay.  But CMOS is likely your worse choice for connecting to the outside world.  There are plenty of TTL FFs out there.  

--  

  Rick C.

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Re: Protecting a CMOS gate input
On 5/15/2020 5:20 PM, Ricky C wrote:
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The FF switches two other sub-circuits alternately on and off.  
The external switch triggers the FF. The debouncing is done in  
the FF itself (although that may not be needed with the series  
resistor and cap at the input). Is that clearer?

Re: Protecting a CMOS gate input
On Friday, May 15, 2020 at 8:02:16 AM UTC-4, Pimpom wrote:
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us.  You might add a front end bipolar transistor, a zener diode or TVS or  
maybe even a gas discharge tube depending on the environment.
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ou are not talking about an SR FF?  If so, you don't really need debouncing
.  Why use CMOS rather than something more static resistant like relays or  
fluidics?
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the other state?  I'm not following what you are doing at all.  I was think
ing the PB would connect to one input of the SR and the other input would b
e the input that resets it.
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 choice for connecting to the outside world.  There are plenty of TTL FFs o
ut there.
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Not really.  Does the switch both set and reset the FF?  If so you must be  
using it on the clk input which means the input does need to be debounced,  
but the FF can't do that.  

What pin of the FF is the switch connected to?  What is on the other two or
 three inputs?  

BTW, if you are using an RC to drive the clock input, you can get multiple  
triggers from any noise in the circuit as the RC will be rising very slowly
.  

If you are using the clock input with the switch, I suggest you debounce it
 with the RC and a Schmitt trigger buffer.  There are some inexpensive rese
t devices that will do the debouncing for you without an RC.  They will acc
ept an input and apply a delay after release.  They are designed as reset d
evices for MCUs.  Essentially they act as retriggerable one shots.  Or you  
could use a 555 timer if you like lots of passives.  I think they use five  
minimum.  

--  

  Rick C.

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Re: Protecting a CMOS gate input
On 5/15/2020 5:54 PM, Ricky C wrote:
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Debouncing is not an issue. And the 4013 FF *can* debounce itself  
with a single R-C combination. The technique is well known and  
I've used it a number of times.

Re: Protecting a CMOS gate input
On Friday, May 15, 2020 at 9:16:08 AM UTC-4, Pimpom wrote:
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uous.  You might add a front end bipolar transistor, a zener diode or TVS o
r maybe even a gas discharge tube depending on the environment.
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 you are not talking about an SR FF?  If so, you don't really need debounci
ng.  Why use CMOS rather than something more static resistant like relays o
r fluidics?
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n the other state?  I'm not following what you are doing at all.  I was thi
nking the PB would connect to one input of the SR and the other input would
 be the input that resets it.
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se choice for connecting to the outside world.  There are plenty of TTL FFs
 out there.
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 be using it on the clk input which means the input does need to be debounc
ed, but the FF can't do that.
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o or three inputs?
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ple triggers from any noise in the circuit as the RC will be rising very sl
owly.
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e it with the RC and a Schmitt trigger buffer.  There are some inexpensive  
reset devices that will do the debouncing for you without an RC.  They will
 accept an input and apply a delay after release.  They are designed as res
et devices for MCUs.  Essentially they act as retriggerable one shots.  Or  
you could use a 555 timer if you like lots of passives.  I think they use f
ive minimum.
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Care to share how the circuit works?  I'm not familiar with any non-Schmitt
 trigger clock input being able to "debounce" itself.  That's why I asked w
hat your circuit is.  I think it is pretty obvious at this point I'm not on
 the same page as you.  

--  

  Rick C.

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Re: Protecting a CMOS gate input
On 5/15/2020 9:21 PM, Ricky C wrote:
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Okay, here it is - somewhat simplified and slightly different  
from my actual circuit, but not in any way that changes the  
operating principles:
https://www.dropbox.com/s/juomu98oyz1vxec/Debounced%20flip-flop.png?dl=0

C2 & R3 do the debouncing, C1 & R2 set the initial state of the  
flip-flop.


Re: Protecting a CMOS gate input
On Friday, May 15, 2020 at 1:02:52 PM UTC-4, Pimpom wrote:
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0

I haven't seen that circuit before.  It's a good one.  I would suggest a co
uple of things if you are interested.  I don't know the environment this is
 going in and I don't know anything about the cable, but in general such an
 external cable can be a source of noise.  So I would not reference the swi
tch to Vcc.  I would use ground.  Since you are using a mechanical switch t
here *will* be bounces, so the polarity of the clock won't matter.  If you  
are concerned it may be connected to something that doesn't bounce you can  
find negative edge D FFs although I only know of one, a 74xx72.  

Using ground as your connection point will provide less noise and better pr
otection.  While Vcc is good for higher frequency decoupling, that is only  
because of the decoupling added to the board.  I don't know if this will be
 significant in your design or not.  

I would definitely use a Zener diode and cap with a high value series resis
tor.  

The world is an ugly place when you are a semiconductor.  

--  

  Rick C.

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Re: Protecting a CMOS gate input
On 5/15/2020 11:18 PM, Ricky C wrote:
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Perhaps I altered the circuit a bit too much in the drawing in an  
attempt for clarity. As mentioned earlier, my previous uses of  
the technique usually had a BJT front end which served as both a  
protective buffer and an inverter. The switch acted between the  
BJT base and ground.

This one is different in that Vdd is ground and Vss is -12V so  
that the pull-up is actually to ground. This makes it convenient  
to connect the switch between the FF input and ground. The cable  
will be a shielded one.

Your suggestion for input protection is noted and appreciated.

Re: Protecting a CMOS gate input
On Friday, May 15, 2020 at 2:15:04 PM UTC-4, Pimpom wrote:
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a couple of things if you are interested.  I don't know the environment thi
s is going in and I don't know anything about the cable, but in general suc
h an external cable can be a source of noise.  So I would not reference the
 switch to Vcc.  I would use ground.  Since you are using a mechanical swit
ch there *will* be bounces, so the polarity of the clock won't matter.  If  
you are concerned it may be connected to something that doesn't bounce you  
can find negative edge D FFs although I only know of one, a 74xx72.
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r protection.  While Vcc is good for higher frequency decoupling, that is o
nly because of the decoupling added to the board.  I don't know if this wil
l be significant in your design or not.
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esistor.

OK, if the input is ground referenced that's great.  The BJT front end will
 also be very good or at least better than directly connecting to CMOS.  

I know I've had bad experiences with inputs from arbitrary sources.  A boar
d I'm building now receives a similar input from a push to talk mic button.
  It goes into an RS-422 receiver through a 4.7K resistor and has all manne
r of self protection built into the chip.  It is specifically designed for  
connection to cables.  This board goes in a rack of equipment and I literal
ly have no idea where the signal comes from.  Never had a board returned fo
r a bad part.  I did have a handful of bad connectors once though.  Connect
ors... ptooey!  

--  

  Rick C.

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Re: Protecting a CMOS gate input

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Ah, it's similar to the feeback debounce used with dual-inverter
bistables. eg:
https://i.stack.imgur.com/yDeFm.png

But your circuit allows the switch be be connected to a
power node at one end, which is a nice feature, also not  
free-running if the switch is held.

--  
  Jasen.

Re: Protecting a CMOS gate input
On 5/16/2020 5:04 PM, Jasen Betts wrote:
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Yeah. And as I explained further in reply to someone else, the  
circuit I'm actually using uses ground as Vdd and -12V as Vss so  
that one end of the switch will be at ground potential.


Re: Protecting a CMOS gate input
On 16/05/2020 2:05 pm, Pimpom wrote:
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Because you want the button signal to clock the flip-flop the RC  
filtering cannot be too aggressive else the clock input rise time will  
be too slow, I reckon CD4013 is good to few dozen us so here is my  
suggestion:

<www.dropbox.com/s/6bq5nftab82er6w/Pimpom_Debounce.jpg?dl=0>

The 330 ohm gives a contact make current of 50mA to help clear oxide  
films and the 10k keeps 1.2mA flowing as long as pressed. In event of  
surge the 0.1uF cap absorbs most of the rise and the 100k in series with  
the clock input keeps the chip safe. Depending on the power supply rate  
of decay you may want to add the ? resistors to protect the chip esd  
diodes from the biggish caps.

piglet


piglet

Re: Protecting a CMOS gate input
On Saturday, May 16, 2020 at 8:02:45 AM UTC-4, Jasen Betts wrote:
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Not free running, but if the switch is held long enough the opening of the  
switch can also bounce and toggle the circuit back to the original state.  
Make the time constant very long to deal with this issue and that sets a li
mit to the time before the FF state can be changed again.  

The inherent limitation of this circuit is that the RC timer and FF are bei
ng used to debounce the control, the FF is also being used to remember a st
ate controlled by the debounced button.  The circuit really needs two FFs,  
one to debounce and one to remember the state.  Then the timeout can be as  
short as the max bounce period and no need to worry about how long a user h
olds the button.  

Rather than two FFs, a simple approach might be to use the RC on the switch
 input and a FF with a Schmitt trigger clock input.  The RC will provide a  
slowly changing input which the Schmitt trigger input will accept without b
ouncing.  Tie the Qn to the D and you get transitions on every button press
.  The only issue is the RC delay is added to detection of the input change
.  For real world push buttons that's not normally an issue.  For machine c
ontrolled switches it may be a problem.  

--  

  Rick C.

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Re: Protecting a CMOS gate input
Ricky C wrote:
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You mean like this, to prevent toggling again on release?


      ^
      |
      |
      R 1M
      |    |
      |   _|_             |-----|
      +---X X---+---------|>   Q|-------
      |         |         |    _|
      |         |     |---|D   Q|---|
      |         |     |   |-----|   |
      |         |     |             |
     === 1uF    R 1K  +------R------|
      |         |     |    100K
      |         |    === 1uF
      |         |     |
      |---------+-----+
                      |
                    -----
                     ---
                      -




Re: Protecting a CMOS gate input
On Sunday, May 17, 2020 at 12:12:18 AM UTC-4, Tom Del Rosso wrote:
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l=0
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I don't think that is quite right.  This way there is no debouncing of the  
voltage from the cap.  The cap has to be on the clock input and then the re
sistors need to be swapped.  1 second RC might be a bit long.  1K from the  
switch to ground with the switch feeding the clock input with 100K and 1.0u
F to power.  This requires a negative edge clock.  Or run the switch to pow
er and let the cap and discharge resistor go to ground.  

The switch can be the only thing on the end of the cable and the switch res
istor can be in the unit as the series limiting resistor.  


    ^
    |
    X |
      |===
    X |
    |                      |-----|
    +--R1K--+----x---------|>   Q|-----
            |    |         |    _|
            |    |     |---|D   Q|---|
            |    |     |   |-----|   |
            |    |1uF  |             |
          R100K ===    +-------------|
            |    |
            |    |
            |    |
            +----+
                 |
               -----
                ---
                 -

The time constant on the Qn feedback to the D is not needed at all then.  T
he RC does the debouncing (as long as the clock input is a Schmitt trigger)
 and the FF just needs to toggle.  

Am I missing something?  

--  

  Rick C.

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Re: Protecting a CMOS gate input
Ricky C wrote:
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That has a slow rise and a slower fall.  The circuit I posted (which was  
one of a compendium of past SED toggle circuits that Win posted) has the  
problem of a slow fall-time if the button is held. I haven't seen any  
debounced toggle circuit that can drive the clock input within its spec,  
and also has adequate protection for an outside connection. They are  
mutually exclusive.

If it was me, I'd use a bipolar in addition to a resistor, cap, and  
zener diode for protection. A pair of biploars can provide the  
non-inverting logic that Pimpom needs, and a pair of bipolars can also  
have a little positive feedback to make it a Schmitt, and provide a very  
fast rise and fall to the FF. (values are just from mental calculation,  
so needs review)

                           ^         ^
                           |         |
                           |         |
                           1k        1k
                           |         |
      ^                    |         |
      |             |----------------x
      |             |      |         |
    | o             |      |         x--------FF clock
   -|               |      |         |
    | o             |      |         |
      |            4.7k    |         c
      |             |      x-------b
      1k            |      |         e
      |             |      |         |
      |             |      c         |
      x----x----x---x----b           |
      |    |    |          e         |
      |    |    |          |         |
      |    |    |          |         |
      1k   10%  ZD         1k        |
      |    |uf  |          |         |
      |    |    |          |         |
      |    |    |          |         |
      V    V    V          V         V


But then I remembered the toggle made with only a Schmitt (I just added  
the 10k at the button, and split the lower 200k and added a cap for  
reset),


                   ^
                   |
                   |
                  200k
                   |
                   |       Schmitt
     | o----10k----x---x-----|>o---x-------
   --|                 |           |
     | o----x---------------1M-----|
            |          |
            |          |                ^
            |         180k              |
            | .01      |                |
           ===         x-------||-------|
            |          |       .01
            |         20k
            |          |
            +----------|
            |
            |
            v

and that means a discreet Schmitt can be a toggle by itself with no  
4013.

I was about to modify the discreet circuit for that, but remembered  
there were already a few discreet toggles in Win's post.

It's probably best of all for ruggedness at the input and it can drive a  
load if the FET is big.


2002, Win Hill, 20A zero-power transistor + MOSFET switch
(Zero power when off, low when on.)
improvements by Jonathan Kirwan, SPICE by Terry Pinnell

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Re: Protecting a CMOS gate input
On Sunday, May 17, 2020 at 5:51:17 PM UTC-4, Tom Del Rosso wrote:
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?dl=0
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Not sure what the issue is with protection, but the debounce I suggested re
quires a schmitt trigger clock input which I stated.  If it has that, the c
ircuit will work.  

Input protection depends on the input spec.  We don't have one, so of cours
e there will be input conditions that will not be met.  State an input spec
 and perhaps I can suggest input conditioning circuits to protect the circu
it.  


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What makes you think this circuit will work reliably?  While it may have a  
schmitt trigger input that is not enough to assure the idle level will be c
lose enough to the threshold voltage to sit in the state given rather than  
revert to a default state.  The threshold value is specified as a wide rang
e that can vary with process and temperature.  


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Definitely the R values need to be tweaked to achieve anything like "low" p
ower when on.  But I guess in comparison to 15 amps even many mA is "low".  
  

--  

  Rick C.

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