Capacitor Discharging with CMOS Gate

No problem.

John

Cool thanks.. Wonderful...That's one less part for my life support system circuit.. :P (Just kidding..)

D from BC British Columbia Canada.

I am not so cheerful about it. It looks to me that there can be a localized heating reliability problem with the CMOS gate output pin.

During the 10uF capacitor's discharge from 14V the 4093 gate's n-channel output mosfet has to dissipate 1mJ of energy in 5ms (assuming a 25mA discharge current). Doing this six times a second means the gate's die will dissipate 6mW, which is certainly not a problem, but this fails to fully settle the question of whether a 350mW peak power level will be damaging.

D can try an acid test, by continuously running the output at full current and supply voltage, and testing for any reduction in the IC's life.

4093 CMOS Schmitt NAND - acid test, _ +14 --+--| \\ | | |0--- +14V '--|_/

We assume the 4093 is powered from the +14V.

The IC's datasheet says the Absolute Maximum package power dissipation is 500mW, at room temp, which implies 350mW will run the die temperature near the maximum rated value. That's not a very good idea, but it may be tolerated OK for a few ms every 167ms.

I'd add the series resistor myself.

Metal migration induced failures?

Note: abs. max "Input or Output Current (DC or *Transient*) per Pin 10mA)

(emphasis added)

Indeed. Particularly with a 15V supply. Sink current is off the gaph (> abs max) at less than 2V Vds. Best regards, Spehro Pefhany

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I don't think that process has the capability to induce metal migration, too weak...20mA never burned up anything.

May be off the graph, but you can see the (Vgs-Vth)^2 characteristic across the Vgs, so that 1.75mA @ 5V => Vth~1.35V and 25mA@Vgs=15V, which is about in line with the curvatures shown there. This makes for 350mW peak and 6msec discharge time for 4% duty. It shouldn't be a problem. He gets about the same discharge time with a series 330R, current peak will be about the same, but peak power reduces to

Yup.. Vdd=14V.

Mmmm.. I might test.. I'm thinking about it.. Testing SOIC chips are a pita without a breakout board..

I think this is one of those problems where the datasheet can't provide every detail, the testing is a pita and putting in a current limiting resistor is the easy way out.

I'm still learning that sometimes it's just not worth the time to dodge only one resistor in a circuit and accept more risk. On the other side, it's artsy to dodge a 'be kind to mosfets' resistor. :)

So yeah say use the resistor ... :)

D from BC British Columbia Canada.

I think the absolute max 'transient' note is conservative when it equals the DC absolute max current. However I'm thinking it's not worth the risk to find out.

D from BC British Columbia Canada.

Actually, even uA currents induce metal migration. Some 30 years ago there was a recognized IC failure mode called Kirkendall voiding. Please Google before calling me a fool.

This is getting interesting enough that i must ask someone who has access to decent test equipment to make some measurements. After 13 years in test labs and 15 years in a job where test instruments are irrelevant i am down to a DMM. Se le guerre.

Metal migration has to do with extraordinarily large current densities and not power dissipation. Those weak little CMOSFETs in the 14000 process can't do it, even the AC family can't do it.

Assuming David's comments are valid, if those old parts have 10u wide metal, then >10mA and certainly 30mA can do it. Best regards, Spehro Pefhany

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If VCC briefly dips for some reason and the cap had enough charge the whole thing might go into latch-up. That would not be cool.

--
Regards, Joerg

http://www.analogconsultants.com/

[snip]

Actually that WOULD be cool ;-)

...Jim Thompson

-- | James E.Thompson, P.E. | mens | | Analog Innovations, Inc. | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | Phoenix, Arizona Voice:(480)460-2350 | | | E-mail Address at Website Fax:(480)460-2142 | Brass Rat | |

| 1962 | America: Land of the Free, Because of the Brave

An open-drain-output would most likely be safe, since their ESD is usually only an N-channel device, thus not path to VDD.

...Jim Thompson

--
|  James E.Thompson, P.E.                           |    mens     |
|  Analog Innovations, Inc.                         |     et      |
|  Analog/Mixed-Signal ASIC's and Discrete Systems  |    manus    |
|  Phoenix, Arizona            Voice:(480)460-2350  |             |
|  E-mail Address at Website     Fax:(480)460-2142  |  Brass Rat  |
|       http://www.analog-innovations.com           |    1962     |
             
         America: Land of the Free, Because of the Brave

Huh? Latch up? The gate is shunting the charged cap to ground. (Charging circuit not shown for clarity) Ideally, I think this shouldn't have an effect on the rails. Non-ideally.. What's it called...ground bounce?? The cap dumps through the gate and blips the Vss rail.

D from BC British Columbia Canada.

Driving the output of a logic gate too far outside the rail voltage can trigger a latchup. This can happen with as little as one diode-drop of excessive voltage. The overvoltage/spike has the effect of activating a "parasitic" structure on the die (a set of P/N junctions not normally part of the circuit, but created in part as a side effect of the way the die is fabricated). If you're unlucky, the parasitic junctions form a PNPN structure, a.k.a. a thyristor or SCR. The spike "turns on" this thyristor, and it begins acting as a short circuit which often can't be reset by any means less drastic than turning off the power entirely.

If the source of the overvoltage has enough charge it and a low enough impedance, the resulting current flow through the parasitic can destroy the chip.

I heard a tale some years ago about an incident involving a new, prototype RISC CPU. The first silicon had just come back from the fab, in one of the special ceramic packages with a quartz lid (to allow for inspection of the chip). Chip was carefully powered up, and lo and behold it worked! One of the developers was so proud that he whipped out a camera and took a photo of the chip in the development board.

Bad move. The camera's flash fired. The flash emitted enough UV (which went through the flash's lens, and through the clear quartz lid of the chip) to cause photoelectric-effect activation of a bunch of the exposed gates on the surface of the chip - a bunch of electrons got knocked loose by the bright light. A whole bunch of parasitic thyristor structures turned on, and (in effect) short-circuited the power supply to ground on multiple places on the chip.

The camera's flash was followed, with no perceptible delay, by a bright flash _inside_ the chip's lid. Boom. Completely dead chip. Do not pass Go, do not collect $200, no saving throw possible.

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Depends on what else is hooked up to that rail. Assume the cap is full. Now some big fat load dips that rail a little. Phssst ... POOF.

--
Regards, Joerg

http://www.analogconsultants.com/

On CD4000 logic that is usually the case.

Once the parasitic SCR has been triggered the impedance of the source doesn't matter anymore. You could completely remove it and the chip would remain in meltdown mode anyhow if the supply rail has enough juice. A loud bang, a stench, smoke alarms wailing, and so on.

What did they do with the guy?

--
Regards, Joerg

http://www.analogconsultants.com/

Afterward, did that developer go to the bar and got drunk? "ssshhhupid flashh... Friffffn flashh... Yah know..I...I ...I... never takn anoother picture in my liffee" :P

D from BC British Columbia Canada.