Now i am designing the clock distribution net work of a digitizer system, The digitizer we design have two channels, each channel can accquire data at 200Ms/s, and now we need that the two channels should be synchronized no more that 100ps.So can any one who has done this kind of design before give me some advice or tell me some ics that fit this design? Welcome new methods too. thanks
clock distribution design
Dec 12, 2005
1 Replies
Have a look at the ON-Semiconductor ECLinPS line. This part offers 9 differential outputs with better than 50psec in-part skew
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If you only need two clock outputs, the
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gets the worst case in-part skew down to 20psec.
------------------ Bill Sloman, Nijmegen
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