Are physical dimensions on 74xxx devices identical ??

74xx devices are packaged in both dual-in-line through the board packages, where the in-line pins are placed on 0.1" (2.54mm grid) and the two lines a re some small multiple of 0.1" apart, and in surface mount packages, where the pins are separated by smaller distances.

So the answer is "no".

see pages 17 to 23 for various different packages for just one part.

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Bill Sloman, Sydney

Do you mean the chips, themselves, or the package dimensions?

Package dimensions are standardized by package name. SOT... etc.

Chips can be quite variable in dimensions and pad locations. ...Jim Thompson

--
| James E.Thompson                                 |    mens     | 
| Analog Innovations                               |     et      | 
| Analog/Mixed-Signal ASIC's and Discrete Systems  |    manus    | 
| San Tan Valley, AZ 85142   Skype: Contacts Only  |             | 
| Voice:(480)460-2350  Fax: Available upon request |  Brass Rat  | 
| E-mail Icon at http://www.analog-innovations.com |    1962     | 
              
I love to cook with wine.     Sometimes I even put it in the food.

DIP packages are always 0.1" centers with 0.3" between the rows.

SOT packages are 50 mil spacing, but there are "wide" and "narrow" footprints for row spacing. Narrow is more common nowadays.

There are other surface mount packages.

Look up some data sheets.

--

John Larkin         Highland Technology, Inc 

jlarkin att highlandtechnology dott com 
http://www.highlandtechnology.com

Just to be clear, the DIP packages that 74xx chips come in, are that size (or for big ones, maybe 0.6" between rows). There are also fine-pitch (metric?) DIP packages, usually seen in consumer goods, from Japanese zaibatsus.

In my junk drawer are 74150, and 74S181, in 0.6" DIP packages. These are obsolete, but DigiKey still has stock of 74LS181, in the 0.6" spacing DIP-24

All answers so far are correct, but here's my take on it:

Any one "DIP" through-hole package is pretty much like any other. The width is either 0.3" or 0.6", the spacing is 0.1".

There are a ton of different surface-mount packages. The SOT packages are the ones that trip me up, because I always seem to place a wide package and order narrow parts, or visa-versa.

Whoever said to read the data sheet -- re-read that post. ALWAYS read the data sheet. Then double-check what you order, to make sure you're getting the package you expect. The only thing more frustrating than shoe-horning a wide SOT chip onto a narrow SOT profile so you can get a prototype board working is looking at a bag full of DIPs and board laid out for a SOT.

--
Tim Wescott 
Control system and signal processing consulting 
www.wescottdesign.com

Only the IC designer would bring this detail up...

--
Tim Wescott 
Control system and signal processing consulting 
www.wescottdesign.com

I've been bitten myself while functioning in another role. When I made hybrids I found out that not only were different manufacturer's

741 chips different sizes, they often were NOT even the same schematic... which causes great grief when they also have different common-mode ranges :-( ...Jim Thompson

--
| James E.Thompson                                 |    mens     | 
| Analog Innovations                               |     et      | 
| Analog/Mixed-Signal ASIC's and Discrete Systems  |    manus    | 
| San Tan Valley, AZ 85142   Skype: Contacts Only  |             | 
| Voice:(480)460-2350  Fax: Available upon request |  Brass Rat  | 
| E-mail Icon at http://www.analog-innovations.com |    1962     | 
              
I love to cook with wine.     Sometimes I even put it in the food.

Thank you each for your responses. We have a board originally designed sometime around

1995, with DIP ICs(the ones that could fit into IC holders) Now, we are planning to re-design the board, replace some of the ICs with SOIC ones and just get rid of some the ICs that we feel are not needed. That is why I asked.

?

I think there were also some DIPs with an 0.4" row spacing. 74xx parts may not have exploited this particular package.

I think that I said it first, but only by virtue of posting from Australia, It is something of a no-brainer.

I don't know about that. Looking at the board and realising that you've mir ror-imaged the pin sequence can be extremely frustrating, not to mention hu miliating. The only thing that saved any shred of my pride was the recollec tion of an extremely experience printed circuit layout person making exactl y the same mistake. As errors of action go, it's pretty horrible, but we ma ke one every half an hour or so, and some of them get missed.

And in my defense, I had to reassign all the pin numbers of the schematic t o get a correct printed circuit layout that worked - going from little-endi an to big-endian within the PCB (without changing any of the external conne ctions).

--
Bill Sloman, Sydney

My very first circuit board layout job was when I was a teaching assistant for the freshman electronics shop class.

Hand taped, on clear plastic, with all those nifty rub-down patterns.

I laid the IC out mirrored, and the instructor didn't catch it until he'd made a bunch of boards. Rather than tossing them, he just had the kiddies solder the chips in from the back side -- "It'll be good for them".

I think I was 17.

--

Tim Wescott 
Wescott Design Services 
http://www.wescottdesign.com

I think we've all done that. Even out CAD guy/librarian did that at the PPoE. We just bent the pins (SMT). Hell, I've even seen datasheets mix up top and bottom views.

The last time I used tape on paper (lathe cutter) was in college, too. All the layouts since have been done by people who do that, on some CAD system or other (though, for the first four or five years, schematics were pencil on velum).

I just did a bad one. Added extra rows to a DIL header but extended the length incorrectly (editing a text-format library file by hand). So the pins were on something like 0.1x0.09 inch pitch instead of

0.1x0.1. Looked fine through CAD and board stuffing until I held that last connector up to the finished board.

I *do* usually check this sort of thing, this time was sort of an experiment in rapid prototyping, basically a one-off test fixture that was likely not worth doing at all if I had to spend a day checking everything. I let the autorouter loose on it too, first time for years.

Worst was one of my first SMT boards, did a 208 pin QFP as 0.5mm instead of 0.4. This was when 4 layer boards were real money and we were poorer, so I tried to bodge it with 208 little wires. Which did not go well.

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John Devereux

Yep, some opto-isolators were release with 0.4" spacing.