Cascading two 74LS90's doesn't work (needs deglitching)

Rocky · 2008-04-25T13:37:34+00:00

Hi there,I am using two 74LS90 ICs cascaded in series to divide down a clocksignal (f=1/60 Hz). A 74LS90 has a divide by 2 and a divide by 5section in it. The 1min period clock pulse is therefore divided upinto: 2min, 5min, 10min and 25min periods.the 2, 5 and 10min periods work OK, but the 25min doesn't. It turnsout to also be 10min rather than 25min.My suspicion is that this problem is highlighted by the followingsentences in Motorola's datasheet:"State changes of the Q outputs do not occursimultaneously because of internal ripple delays. Therefore,decoded output signals are subject to decoding spikes andshould not be used for clocks or strobes."I don't have a DSO to see if there are glitches on the divide by 5output from the first 74LS90. (I just have an analog CRO), so I amassuming there are glitches that are causing this problem.I tried placing a single pole passive LPF in series from the div5output to the CLK input of the 2nd 74LS90 to no avail. It seemed toresult in random periods coming from the outputs of the 2nd 74LS90.I kept the resistor low enough (a few hundred ohms) so the inputcurrent didn't stuff the logic levels up. And I tried capacitors of0.1uF, 0.68uF and even 100uF (this 100uF stopped the lines fromtoggling altogether !). All the set and preset pins on the 74LS90sare tied low as required.So is it possible to deglitch the output of a 74LS90 ?regardsPeter

Apr 25, 2008 42 Replies

Rate this thread:

JosephKK 18 years ago

Agreed.

There is a limit to how fine a grain that it can be applied.

many ways.

And that is the truth.

Vote

John Fields 18 years ago

There are no glitches on the Q outputs of the counters. What Motorola is talking about is that since the counters\' outputs don\'t occur simultaneously, if you use glue logic to decode a particular state that decoded output will have glitches in it and can\'t be used as a clock or a strobe. How about posting a schematic of your circuit? JF

Vote