I've scored a huge bunch of 74LS series logic off Ebay, and since I'd like to learn more about digital design I'm thinking of building a classic digital clock circuit out of the logic. The assortment only contains 74LS93 4 bit counters, and I hope to use AND gates to decode the outputs to provide reset and clock pulses at the appropriate times. While the circuit simulates fine in the HADES software, my concern is that since the 74LS93 is a ripple counter the outputs will glitch and make this setup unusable in practice. In the "TTL Cookbook" the author states that some ripple counter states are glitch free, while others will cause problems, but doesn't seem to clarify the issue. I'm wondering if anyone here with more experience could tell if this kind of circuit is doomed to failure, or if it could work. The shipment hasn't arrived yet so unfortunately I can't set up a prototype just yet. Thanks for any advice!
If you use a NAND gate to decode a state of a ripple counter (for example, run Q2 and Q8 into the gate to decode "10" and reset the counter there, to count from 0 to 9) that decode is glitch-free. No state below 10 produces an output.
Thanks for the reply. Since the LS93 requires a positive trigger to reset, this should still work if I invert the outputs, correct? While I've constructed the functional equivalent of an AND gate, it would be the NAND part of it that's getting the glitches, if that makes any sense. It's really a NOT-NAND gate I guess.
And you can always put inverse of the clock into the NAND gate so that it only activated when the clock is low. As long as the propagation delay of the ripple counter is less than half a clock period (or more accurately less than the high time of the clock) you are assured a glitch free output. The techique you described above works well for simple modulo counters but if you are decoding other states as well the reset may well cause glitches on those signals when the counter is reset as some bits will reset before others.
It wouldn't matter whether the decode gate was a NAND or an AND. The point is that the first time that Q2 and Q8 come up together is at count 10. That's true for any terminal count decode on a ripple counter.
If you are decoding intermediate states and want to produce a clean pulse from that then it is important as lower order bits in the counter will change state before high order ones. For a terminal count it's fine, effectively the highest order bit changes last which causes the decoder to reset the counter, the bits then return to zero and the reset pulse automatically negates.
If this is a mains (50/60 Hz) operated clock, you are going to need a few divide by 5, by 6 and by 10 division stages, which should be easy to implement with 7493 without external gatings.
The 7393 contains a divide by two and a separate divide by eight section with a common reset input.
The chip contains two reset inputs (reset performed when both high) and all the required division ratios only contain two "1" bits at the end of the count, the internal reset gating is sufficient for /5/6/10 operation. The divide by 5 and by 6 can be implemented using only the last three flip flops.
Since the chip counts on the falling edge of the clock, simply connect the clock input to the Q3 output of the previous stage, thus, when for instance the send counter reached "60 s", the ten second Q3 counter drops due to the forced reset to zero, incrementing the minute counter.
While a ripple counter will certainly operate as a binary frequency divider at much higher frequencies than used for decoding certain complex states (e.g. for reset).
In this case, the clock periods are huge compared to the logic propagation delay, so no problems should be expected.
While certainly there would be a risk for glitches, if the count for the following stage is derived from some internal reset circuitry, however, since the count for the following stage is taken from the last flip flop, which has in this case already been stable for more than one clock cycle, the Q3 output of 7493 is not going to produce glitches, even due to asynchronous reset.
You may have a lot of problems if you try to connect three 7493 as a
12 bit ripple counter and use external circuitry to perform a (say) divide by 3579 operation at frequencies above a few MHz.
In such kind of operation, the propagation delay through the flip flop chain must be less than half of the clock cycle period, assuming that the reset signal is strobed by the clock signal.
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